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72215

更新时间: 2023-12-20 18:44:26
品牌 Logo 应用领域
瑞萨 - RENESAS 先进先出芯片
页数 文件大小 规格书
17页 308K
描述
512 x 18 SyncFIFO, 5.0V

72215 数据手册

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IDT72205LB/72215LB/72225LB/72235LB/72245LBCMOSSyncFIFOTM  
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18  
COMMERCIALANDINDUSTRIAL  
TEMPERATURERANGES  
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext READ EXPANSION OUT (RXO)  
writecycle,theHalf-FullFlaggoesLOWandwillremainsetuntilthedifference  
In the Daisy Chain Depth Expansion configuration, Read Expansion In  
betweenthewritepointerandreadpointerislessthanorequaltoonehalfof (RXI)isconnectedtoReadExpansionOut(RXO)ofthepreviousdevice.This  
thetotalmemoryofthedevice. TheHalf-FullFlag(HF)isthenresettoHIGH outputactsasasignaltothenextdeviceintheDaisyChainbyprovidingapulse  
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is whenthepreviousdevicereadsfromthelastlocationofmemory.  
asynchronous.  
IntheDaisyChainDepthExpansion mode, WXIisconnectedtoWXOof DATAOUTPUTS(Q0-Q17)  
thepreviousdevice. ThisoutputactsasasignaltothenextdeviceintheDaisy  
Chainbyprovidingapulsewhenthepreviousdevicewritestothelastlocation  
ofmemory.  
Q0-Q17 aredataoutputsfor18-bitwidedata.  
tRS  
t
RSR  
tRSS  
t
RSF  
t
t
RSF  
RSF  
(1)  
= 1  
Q0 - Q17  
2766 drw 06  
= 0  
NOTES:  
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.  
2. The clocks (RCLK, WCLK) can be free-running during reset.  
Figure 4. Reset Timing(2)  
8
MARCH 2013  

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