Datasheet > 存储 > SRAM> 71V416YL12YG2

71V416YL12YG2

更新时间： 2024-02-09 17:58:52

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器光电二极管内存集成电路
页数	文件大小	规格书
9页	137K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44

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技术参数
数据手册

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71V416YL12YG2 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	SOJ, SOJ44,.44
Reach Compliance Code：	compliant	风险等级：	5.57
Base Number Matches：	1

71V416YL12YG2 数据手册

IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM

for Automotive Applications 4 Meg (256K x 16-Bit)

Automotive Temperature Ranges

Timing Waveform of Read Cycle No. 2⁽¹⁾

ADDRESS

(3)

OHZ

(3)

OLZ

(2)

ACS

(3)

CHZ

CLZ

BLE

BHE

(2)

(3)

BHZ

BLZ

DATAOUT

DATAOUT VALID

Supply

Current

6817 drw 07

NOTES:

1. WE is HIGH for Read Cycle.

2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.

3. Transition is measured ±200mV from steady state.

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)^(1,2,4)

ADDRESS

(2)

(5)

CHZ

BHE

BLE

BHZ

(5)

WHZ

(5)

(3)

DATAOUT

DATAIN

PREVIOUS DATA VALID

DATA VALID

DATAIN VALID

6817 drw 08

NOTES:

1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.

2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data

to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as

short as the specified tWP.

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

6.462

1...3 4 567 8 9

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