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71V416YL12PHG8 PDF预览

71V416YL12PHG8

更新时间: 2023-02-26 15:40:57
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
9页 478K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44

71V416YL12PHG8 数据手册

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IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM  
4 Meg (256K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
AC Electrical Characteristics  
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)  
71V416S/L10(2)  
71V416S/L12  
71V416S/L15  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
____  
____  
____  
t
RC  
AA  
ACS  
Read Cycle Time  
10  
12  
15  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
t
Address Access Time  
Chip Select Access Time  
10  
12  
15  
____  
____  
____  
t
10  
12  
15  
(1)  
CLZ  
____  
____  
____  
t
Chip Select Low to Output in Low-Z  
Chip Select High to Output in High-Z  
Output Enable Low to Output Valid  
Output Enable Low to Output in Low-Z  
Output Enable High to Output in High-Z  
Output Hold from Address Change  
Byte Enable Low to Output Valid  
4
4
4
(1)  
____  
____  
____  
tCHZ  
5
6
7
____  
____  
____  
tOE  
5
6
7
(1)  
(1)  
____  
____  
____  
tOLZ  
0
0
0
____  
____  
____  
t
OHZ  
OH  
BE  
5
6
7
____  
____  
____  
t
4
4
4
____  
____  
____  
t
5
6
7
(1)  
____  
____  
____  
tBLZ  
Byte Enable Low to Output in Low-Z  
Byte Enable High to Output in High-Z  
0
0
0
(1)  
____  
____  
____  
tBHZ  
5
6
7
WRITE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
WC  
AW  
CW  
BW  
AS  
WR  
WP  
DW  
DH  
Write Cycle Time  
10  
8
8
8
0
0
8
5
0
12  
8
8
8
0
0
8
6
0
15  
10  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
Address Valid to End of Write  
Chip Select Low to End of Write  
Byte Enable Low to End of Write  
Address Set-up Time  
t
t
t
t
Address Hold from End of Write  
Write Pulse Width  
0
t
10  
7
t
Data Valid to End of Write  
Data Hold Time  
t
0
(1)  
OW  
t
Write Enable High to Output in Low-Z  
Write Enable Low to Output in High-Z  
3
3
3
(1)  
WHZ  
____  
____  
____  
t
6
7
7
ns  
6442 tbl 10  
NOTE:  
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.  
2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only.  
Timing Waveform of Read Cycle No. 1(1,2,3)  
tRC  
ADDRESS  
t
AA  
tOH  
tOH  
DATAOUT VALID  
DATAOUT  
PREVIOUS DATAOUT VALID  
NOTES:  
6442d06  
1. WE is HIGH for Read Cycle.  
2. Device is continuously selected, CS is LOW.  
3. OE, BHE, and BLE are LOW.  
6.42  
5

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