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71V416YL12PHG8

更新时间: 2023-02-26 15:40:57
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
9页 478K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, 0.400 INCH, ROHS COMPLIANT, TSOP2-44

71V416YL12PHG8 数据手册

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IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM  
4 Meg (256K x 16-Bit)  
Commercial and Industrial Temperature Ranges  
DC Electrical Characteristics  
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)  
IDT71V416  
Symbol  
|ILI  
|ILO  
Parameter  
Input Leakage Current  
Test Conditions  
Min.  
Max.  
5
Unit  
µA  
µA  
V
___  
|
V
CC = Max., VIN =  
DD = Max., CS = VIH, VOUT = VSS to VDD  
OL = 8mA, VDD = Min.  
OH = -4mA, VDD = Min.  
VSS to VDD  
___  
___  
|
Output Leakage Current  
Output Low Voltage  
Output High Voltage  
V
5
VOL  
I
0.4  
___  
VOH  
I
2.4  
V
6442 tbl 07  
DC Electrical Characteristics(1, 2, 3)  
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)  
71V416S/L12  
71V416S/L15  
71V416S/L10  
Com'l.  
Ind.(5)  
200 200  
Symbol  
Parameter  
Dynamic Operating Current  
CS < VLC, Outputs Open, VDD = Max., f = fMAX  
Unit  
Com'l.  
Ind.  
180  
170  
60  
Com'l.  
170  
160  
50  
Ind.  
170  
160  
50  
ICC  
S
L
S
L
S
L
180  
170  
60  
mA  
(4)  
180  
70  
50  
20  
10  
70  
20  
ISB  
Dynamic Standby Power Supply Current  
CS > VHC, Outputs Open, VDD = Max., f = fMAX  
mA  
(4)  
45  
45  
40  
40  
ISB1  
Full Standby Power Supply Current (static)  
20  
20  
20  
20  
mA  
CS > VHC, Outputs Open, VDD = Max., f = 0(4)  
10  
10  
10  
10  
6442 tbl 08  
NOTES:  
IDT71V416S/71V416L  
1. All values are maximum guaranteed values.  
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).  
3. Power specifications are preliminary.  
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.  
5. Standard power 10ns (S10) speed grade only.  
3.3V  
320  
AC Test Loads  
+1.5V  
50  
OUT  
DATA  
I/O  
Z0 = 50Ω  
5pF*  
350Ω  
30pF  
6442 drw 03  
6442 drw 04  
Figure 1. AC Test Load  
*Including jig and scope capacitance.  
Figure 2. AC Test Load  
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)  
7
6
AC Test Conditions  
tAA,  
t
ACS  
5
4
3
(Typical, ns)  
Input Pulse Levels  
GND to 3.0V  
2
1
Input Rise/Fall Times  
Input Timing Reference Levels  
Output Reference Levels  
AC Test Load  
1.5ns  
1.5V  
1.5V  
180  
8 20 40 60 80 100 120 140 160  
CAPACITANCE (pF)  
200  
6442 drw 05  
Figures 1,2 and 3  
Figure 3. Output Capacitive Derating  
6442 tbl 09  
6.442  

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