Datasheet > 71V3557SA85BQ

71V3557SA85BQ

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	523K
描述
ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165

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71V3557SA85BQ 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	13 X 15 MM, FBGA-165
针数：	165	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.58	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH ARCHITECTURE	最大时钟频率 (fCLK)：	90 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B165
JESD-609代码：	e0	长度：	15 mm
内存密度：	4718592 bit	内存集成电路类型：	ZBT SRAM
内存宽度：	36	湿度敏感等级：	3
功能数量：	1	端子数量：	165
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX36
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TBGA	封装等效代码：	BGA165,11X15,40
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, THIN PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	225
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	最大待机电流：	0.04 A
最小待机电流：	3.14 V	子类别：	SRAMs
最大压摆率：	0.225 mA	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	20
宽度：	13 mm

71V3557SA85BQ 数据手册

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Pin Definitions ⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

A⁰-A¹⁷

Address Inputs

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,

ADV/LD low, CEN low, and true chip enables.

ADV/LD

Advance / Load

N/A

ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it

is sampled low at the rising edge of clock with the chip selected. When ADV/ is low with the chip

deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/LD is

sampled high.

R/W

Read / Write

Clock Enable

N/A

R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write

access to the memory array. The data bus activity for the current cycle takes place one clock cycle later.

LOW

Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock

are ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if

the low to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge

of clock.

CEN

Individual Byte

Write Enables

LOW

Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write

cycles (When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW¹-BW⁴) must be valid.

The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when

R/W is sampled high. The appropriate byte(s) of data are written into the device one cycle later. BW¹-BW4

can all be tied low if always doing write to the entire 36-bit word.

BW¹-BW4

Chip Enables

Synchronous active low chip enable. CE¹and CE²are used with CE²to enable the IDT71V3557/59. (CE¹or

CE²sampled high or CE²sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect

cycle. The ZBT^TMhas a one cycle deselect, i.e., the data bus will tri-state one clock cycle after deselect is

initiated.

CE¹CE

CE²

Chip Enable

Clock

HIGH

N/A

Synchronous active high chip enable. CE²is used with CE¹and CE²to enable the chip. CE²has inverted

polarity but otherwise identical to CE¹and CE².

CLK

This is the clock input to the IDT71V3557/59. Except for OE, all timing references for the device are made

with respect to the rising edge of CLK.

I/O⁰-I/O³¹

I/O^P1-I/O^P4

Data Input/Output

Linear Burst Order

Output Enable

I/O

N/A

Data input/output (I/O) pins. The data input path is registered, triggered by the rising edge of CLK. The data

output path is flow-through (no output register).

LOW

Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low

the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation..

LBO

Asynchronous output enable. OE must be low to read data from the 71V3557/59. When OE is HIGH the I/O

pins are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In

normal operation, OE can be tied low.

TMS

TDI

Test Mode Select

Test Data Input

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an

internal pullup.

Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,

while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.

TCK

TDO

Test Clock

N/A

Serial output of registers placed between TDI and TDO. This output is active depending on the state of the

TAP controller.

Test Data Output

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset

occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can

be left floating. This pin has an internal pullup.

JTAG Reset

(Optional)

LOW

HIGH

TRST

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3557/3559 to

its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal

pulldown.

Sleep Mode

V^DD

V^DDQ

V^SS

Power Supply

Ground

N/A

3.3V core power supply.

3.3V I/O Supply.

Ground.

5282 tbl 02

NOTE:

1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.

6.422

123 4 5 6 7...28

中文翻译

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与71V3557SA85BQ相关器件

型号	品牌	获取价格	描述	数据表
71V3557SA85BQ8	IDT	获取价格	SRAM
71V3557SA85BQG8	IDT	获取价格	SRAM
71V3557SA85BQGI	IDT	获取价格	Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165
71V3557SA85BQGI8	IDT	获取价格	SRAM
71V3557SA85BQI	IDT	获取价格	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165
71V3557SA85BQI8	IDT	获取价格	SRAM
71V3557SA85PFGI	IDT	获取价格	Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100
71V3558	RENESAS	获取价格	3.3V 256K x 18 ZBT Synchronous PipeLined SRAM w/3.3V I/O
71V3558S100BGI	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119
71V3558S100BGI8	IDT	获取价格	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119

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