Datasheet > 71V2578S150PF9

71V2578S150PF9

更新时间： 2023-01-03 05:04:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	620K
描述
TQFP-100, Tray

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中文翻译

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数据手册

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71V2578S150PF9 数据手册

128K X 36, 256K X 18

IDT71V2576S

IDT71V2578S

IDT71V2576SA

IDT71V2578SA

3.3VSynchronousSRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V2576/78 are high-speed SRAMs organized as 128K x

36/256Kx18.TheIDT71V2576/78SRAMscontainwrite,data,address

andcontrolregisters. InternallogicallowstheSRAMtogenerateaself-

timedwritebaseduponadecisionwhichcanbeleftuntiltheendofthewrite

cycle.

◆

Supports high system speed:

CommercialandIndustrial:

– 150MHz 3.8ns clock access time

– 133MHz 4.2ns clock access time

LBO input selects interleaved or linear burst mode

◆

Theburstmodefeatureoffersthehighestlevelofperformancetothe

◆

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite systemdesigner,astheIDT71V2576/78canprovidefourcyclesofdata

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1 operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

compliant) datawillbeavailabletotheuseronthenextthreerisingclockedges. The

Packaged in a JEDEC Standard 100-pin plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack(TQFP),119ballgridarray(BGA)and165finepitchball andthe LBO inputpin.

grid array (fBGA)

forasingleaddress presentedtotheSRAM. Aninternalburstaddress

counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

◆

The IDT71V2576/78 SRAMs utilize IDT’s latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pinthinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and 165 fine pitch ball grid array (fBGA).

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

, CS

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

BWE

BW , BW

(1)

, BW

CLK

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

ADV

ADSC

ADSP

LBO

TMS

TDI

Synchronous

N/A

TCK

TDO

TRST

Test Clock

Test Data Output

Synchronous

Asynchronous

Synchronous

N/A

JTAG Reset (Optional)

Sleep Mode

I/O

-I/O31, I/OP1-I/OP4

DD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

N/A

4876 tbl 01

NOTE:

JUNE 2003

1. BW3 and BW4 are not applicable for the IDT71V2578.

DSC-4876/09

12 3 4 5 6 7...22

中文翻译

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与71V2578S150PF9相关器件

型号	品牌	获取价格	描述	数据表
71V2578S150PFG	IDT	获取价格	TQFP-100, Tray
71V2578YS133BG8	IDT	获取价格	PBGA-119, Reel
71V257975BQ	IDT	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PBGA165
71V257975PF	IDT	获取价格	Standard SRAM, 256KX18, 7.5ns, CMOS, PQFP100
71V257980BGI	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA119
71V257980BQ	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PBGA165
71V257980PFI	IDT	获取价格	Standard SRAM, 256KX18, 8ns, CMOS, PQFP100
71V257985BG	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA119
71V257985BQ	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165
71V257985BQI	IDT	获取价格	Standard SRAM, 256KX18, 8.5ns, CMOS, PBGA165

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