IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration — 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
NC(2)
ADV/LD
A
A
A
2
3
2
9
NC
NC
16
CE
NC
NC
2
CE
7
A
DD
V
12
15
A
A
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
NC(2)
I/O
BW
2
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
V
R/W
DDQ
V
DD
DD
V
DD
DDQ
V
DD(1)
SS
DD(1)
V
V
V
24
I/O
26
I/O
SS
6
I/O
7
I/O
K
L
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
BW
1
DDQ
28
SS
V
SS
SS
SS
3
DDQ
1
M
N
P
R
T
V
I/O
V
V
V
I/O
V
CEN
29
I/O
30
I/O
SS
V
1
A
2
I/O
I/O
I/O
31
I/O
P4
SS
V
0
A
0
I/O
I/OP1
,
5
DD
11
VDD(1)
13
A
NC
A
V
NC
LBO
(5)
10
A
14
A
NC
NC
A
NC
NC/ZZ
(3)
(3)
(3)
(3)
(3,4)
DDQ
V
DDQ
V
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
NC/TRST
4875 drw 13a
TopView
Pin Configuration — 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
NC(2)
3
2
9
NC
NC
CE2
NC
NC
NC
CE
2
ADV/LD
7
A
DD
V
13
17
A
A
8
SS
SS
SS
SS
SS
SS
SS
P1
I/O
I/O
NC
NC
V
V
V
NC
V
V
V
V
9
I/O
7
I/O
CE
1
NC
DDQ
V
6
I/O
DDQ
5
NC
V
OE
10
I/O
G
H
J
NC
NC
I/O
NC(2)
BW
2
11
I/O
SS
SS
4
I/O
NC
V
V
V
V
V
V
NC
DDQ
R/W
DD(1)
SS
DD(1)
SS
DDQ
V
DD
V
DD
V
DD
V
V
12
I/O
3
I/O
K
L
NC
CLK
NC
NC
13
I/O
SS
2
I/O
NC
V
NC
BW
1
DDQ
15
14
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
I/O
V
V
V
V
V
V
NC
CEN
SS
SS
1
A
1
I/O
I/O
NC
NC
P2
0
A
0
I/O
NC
I/O
NC
,
5
DD
V
12
A
NC
NC
DDQ
A
V
DD(1)
NC
LBO
(5)
10
15
14
A
11
A
A
A
NC
NC/ZZ
(3)
(3)
(3)
(3)
(3,4)
DDQ
V
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
V
NC/TRST
4875 drw 13b
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.
6.42
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