IDT71V016SA, 3.3V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71V016SA10(2)
71V016SA12
71V016SA15
71V016SA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
20
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
10
12
15
20
____
____
____
____
t
Chip Select Access Time
Chip Select Low to Output in Low-Z
10
12
15
20
____
____
____
____
(1)
CLZ
4
4
5
5
t
____
____
____
____
(1)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
t
CHZ
____
____
____
____
tOE
5
6
7
8
(1)
(1)
____
____
____
____
0
0
0
0
t
OLZ
____
____
____
____
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
ns
t
OHZ
OH
BE
t
4
—
4
—
4
—
4
—
____
t
—
5
—
6
—
7
8
____
____
____
____
(1)
0
0
0
0
t
BLZ
____
____
____
____
(1)
Byte Enable High to Output in High-Z
5
6
6
8
ns
t
BHZ
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
BW
AS
WR
WP
DW
DH
Write Cycle Time
10
7
7
7
0
0
7
5
0
12
8
8
8
0
0
8
6
0
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
t
t
t
t
Address Hold from End of Write
Write Pulse Width
0
0
t
10
7
12
9
t
Data Valid to End of Write
Data Hold Time
t
0
0
____
____
____
____
(1)
OW
Write Enable High to Output in Low-Z
3
3
3
3
t
(1)
WHZ
____
____
____
____
Write Enable Low to Output in High-Z
5
6
6
8
ns
t
NOTES:
3834 tbl 10
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 0° C to +70°C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
3834 drw 06
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
6.42
5