18Mb Pipelined
QDR™II SRAM
Burst of 2
IDT71P72804
IDT71P72604
Features
Description
The IDT QDRIITM Burst of two SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with two data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
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18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
Supports concurrent transactions
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Dual Echo Clock Output
2-Word Burst on all SRAM accesses
DDR (Double Data Rate) MultiplexedAddress Bus
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One Read and One Write request per clock cycle
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DDR (Double Data Rate) Data Buses
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Two word burst data per clock on each port
Four word transfers per clock cycle (2 word bursts
on 2 ports)
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Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
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Scalable output drivers
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Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
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Output Impedance adjustable from 35 ohms to 70
ohms
The QDRII has a single DDR address bus with multiplexed read
and write addresses. All read addresses are received on the first half of
the clock cycle and all write addresses are received on the second half
of the clock cycle. The read and write enables are received on the first
half of the clock cycle. The byte and nibble write signals are received on
both halves of the clock cycle simultaneously with the data they are
controlling on the data input bus.
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Commercial and IndustrialTemperature Ranges
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Functional Block Diagram
(Note1)
(Note1)
(Note1)
DATA
DATA
REG
D
REG
WRITE DRIVER
(Note2)
(Note3)
ADD
REG
(Note2)
SA
(Note4)
(Note4)
(Note1)
18M
MEMORY
ARRAY
Q
R
W
BWx
CTRL
LOGIC
K
CLK
GEN
CQ
K
CQ
C
SELECT OUTPUT CONTROL
C
6109 drw 16
Notes
1) Represents 18 signal lines for x18, and 36 signal lines for x36
2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 2 signal lines for x18, and 4r signal lines for x36.
4) Represents 36 signal lines for x18, and 72 signal lines for x36.
APRIL 2006
1
©2005 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
DSC-6109/0A