Datasheet > 71P72604S167BQG

71P72604S167BQG

更新时间： 2024-10-02 21:05:23

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
21页	869K
描述
CABGA-165, Tray

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技术参数
数据手册

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71P72604S167BQG 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	CABGA
包装说明：	13 X 15 MM, GREEN, FPBGA-165	针数：	165
Reach Compliance Code：	unknown	ECCN代码：	3A991
HTS代码：	8542.32.00.41	风险等级：	5.8
最长访问时间：	0.5 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	167 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	524288 words
字数代码：	512000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	512KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最小待机电流：	1.7 V	子类别：	SRAMs
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

71P72604S167BQG 数据手册

18Mb Pipelined

QDR™II SRAM

Burst of 2

IDT71P72804

IDT71P72604

Features

Description

The IDT QDRII^TMBurst of two SRAMs are high-speed synchro-

nous memories with independent, double-data-rate (DDR), read and

write data ports. This scheme allows simultaneous read and write

access for the maximum device throughput, with two data items passed

with each read or write. Four data word transfers occur per clock

cycle, providing quad-data-rate (QDR) performance. Comparing this

with standard SRAM common I/O (CIO), single data rate (SDR) de-

vices, a four to one increase in data access is achieved at equivalent

clock speeds. Considering that QDRII allows clock speeds in excess of

standard SRAM devices, the throughput can be increased well beyond

four to one in most applications.

◆

18Mb Density (1Mx18, 512kx36)

Separate, Independent Read and Write Data Ports

Supports concurrent transactions

◆

Dual Echo Clock Output

2-Word Burst on all SRAM accesses

DDR (Double Data Rate) MultiplexedAddress Bus

One Read and One Write request per clock cycle

◆

DDR (Double Data Rate) Data Buses

Two word burst data per clock on each port

Four word transfers per clock cycle (2 word bursts

on 2 ports)

◆

Depth expansion through Control Logic

HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

◆

Scalable output drivers

Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V.

Output Impedance adjustable from 35 ohms to 70

ohms

The QDRII has a single DDR address bus with multiplexed read

and write addresses. All read addresses are received on the first half of

the clock cycle and all write addresses are received on the second half

of the clock cycle. The read and write enables are received on the first

half of the clock cycle. The byte and nibble write signals are received on

both halves of the clock cycle simultaneously with the data they are

controlling on the data input bus.

◆

Commercial and IndustrialTemperature Ranges

1.8V Core Voltage (VDD)

165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

JTAG Interface

Functional Block Diagram

(Note1)

DATA

REG

WRITE DRIVER

(Note2)

(Note3)

ADD

REG

(Note2)

(Note4)

(Note1)

18M

MEMORY

ARRAY

BWx

CTRL

LOGIC

CLK

GEN

SELECT OUTPUT CONTROL

6109 drw 16

Notes

1) Represents 18 signal lines for x18, and 36 signal lines for x36

2) Represents 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 2 signal lines for x18, and 4r signal lines for x36.

4) Represents 36 signal lines for x18, and 72 signal lines for x36.

OCTOBER 2008

DSC-6109/0A

12 3 4 5 6 7...21

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与71P72604S167BQG相关器件

型号	品牌	获取价格	描述	数据表
71P72604S167BQG8	IDT	获取价格	CABGA-165, Reel
71P72604S167BQGI	IDT	获取价格	CABGA-165, Tray
71P72604S200BQ	IDT	获取价格	CABGA-165, Tray
71P72604S200BQG	IDT	获取价格	CABGA-165, Tray
71P72604S200BQG8	IDT	获取价格	CABGA-165, Reel
71P72604S200BQI	IDT	获取价格	CABGA-165, Tray
71P72604S250BQ	IDT	获取价格	CABGA-165, Tray
71P72604S250BQG	IDT	获取价格	CABGA-165, Tray
71P72604S250BQG8	IDT	获取价格	CABGA-165, Reel
71P72604S250BQI	IDT	获取价格	CABGA-165, Tray

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