Advance
Information
IDT71P71204
IDT71P71104
IDT71P71804
IDT71P71604
18Mb Pipelined
DDR™II SRAM
Burst of 2
Features
Description
TM
◆
◆
◆
◆
◆
18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)
The IDT DDRII Burst of two SRAMs are high-speed synchronous
memories with a double-data-rate (DDR), bidirectional data port. This
scheme allows maximization of the bandwidth on the data bus by pass-
ing two data items per clock cycle. The address bus operates at single
data rate speeds, allowing the user to fan out addresses and ease
system design while maintaining maximum performance on data trans-
fers.
Common Read and Write Data Port
Dual Echo Clock Output
2-Word Burst on all SRAM accesses
Multiplexed Address Bus
-
One Read or One Write request per clock cycle
◆
DDR (Double Data Rate) Data Bus
-
Two word bursts data per clock
The DDRII has scalable output impedance on its data output bus and
echo clocks, allowing the user to tune the bus for low noise and high
performance.
◆
◆
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals
from 1.4V to 1.9V.
All interfaces of the DDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, indepen-
dent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
◆
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level
from 1.4V to 1.9V.
Output Impedance adjustable from 35 ohms to 70
ohms
-
◆
◆
◆
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Clocking
The DDRII SRAM has two sets of input clocks, namely the K, K clocks
and the C, C clocks. In addition, the DDRII has an output “echo” clock,
CQ, CQ.
The K and K clocks are the primary device input clocks. The K clock
is used to clock in the control signals (LD, R/W and BWx or NWx), the
address, and the first word of the data burst during a write operation.
Functional Block Diagram
DATA
REG
(Note 1)
WRITE DRIVER
(Note2)
ADD
REG
(Note2)
SA
SA
0
(Note1)
(Note4)
(Note1)
18M
MEMORY
ARRAY
DQ
LD
R/W
BWx
CTRL
LOGIC
(Note3)
K
CLK
GEN
CQ
K
CQ
C
SELECT OUTPUT CONTROL
C
6112 drw 16
Notes
1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36
2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.
3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2
signal lines.
4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.
MAY 2004
1
©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
DSC-6112/00
5秒后页面跳转
塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
英特尔震撼发布：128核心256线程的至强6性能核处理器
SK海力士量产12层HBM3E，容量高达36GB
意法半导体传感器驱动Sphere，开启沉浸式电影新时代
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
