Datasheet > 7143SA45J

7143SA45J

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

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7143SA45J 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE⁽⁵⁾

tRC

ADDRESS

tOH

DATAOUT

PREVIOUS DATA VALID

DATA VALID

BUSYOUT

(3,4)

2746 drw 07

tBDD

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE⁽⁵⁾

(4)

tACE

(4)

(2)

tAOE

tHZ

(1)

(2)

tLZ

tHZ

DATAOUT

VALID DATA

(1)

tLZ

tPU

tPD

ICC

CURRENT

50%

ISB

2746 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is deasserted first, OE or CE.

3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no

relationship to valid output data.

4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.

5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.

6.42

1...5 6 789 10 11...16

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