Datasheet > 7143SA45J

7143SA45J

更新时间： 2023-01-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 45ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68

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7143SA45J 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Data Retention Characteristics

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

7133LA/7143LA

Symbol

Parameter

CC for Data Retention

Test Condition

Min.

2.0

___

Typ.⁽¹⁾

Max.

Unit

___

VDR

CC = 2V

CE > VHC

IN > VHC or < VLC

CCDR

Data Retention Current

µA

MIL. & IND.

100

4000

___

COM'L.

100

1500

(3)

CDR

___

Chip Deselect to Data Retention Time

Operation Recovery Time

(3)

(2)

___

2746 tbl 08

NOTES:

1. Vcc = 2V, TA = +25°C, and are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by device characterization but is not production tested.

Data Retention Waveform

DATA RETENTION MODE

DR > 2V

VCC

4.5V

tCDR

VDR

VIH

2746 drw 05

AC Test Conditions

Input Pulse Levels

GND to 3.0V

1250Ω

Input Rise/Fall Times

5ns Max.

1.5V

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

1.5V

775Ω

30pF

Figures 1, 2 and 3

2746 tbl 09

Figure 1. AC Output Test Load

270Ω

1250Ω

BUSY

DATAOUT

775Ω

30pF

5pF*

2746 drw 06

Figure 2. Output Load

Figure 3. BUSY Output Load

(for tLZ, tHZ, tWZ, tOW)

(IDT7133 only)

*Including scope and jig

6.42

1...3 4 567 8 9...16

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