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7134LA35JB8 PDF预览

7134LA35JB8

更新时间: 2023-05-15 00:00:00
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
11页 99K
描述
Multi-Port SRAM, 4KX8, 35ns, CMOS, PQCC52

7134LA35JB8 数据手册

 浏览型号7134LA35JB8的Datasheet PDF文件第3页浏览型号7134LA35JB8的Datasheet PDF文件第4页浏览型号7134LA35JB8的Datasheet PDF文件第5页浏览型号7134LA35JB8的Datasheet PDF文件第7页浏览型号7134LA35JB8的Datasheet PDF文件第8页浏览型号7134LA35JB8的Datasheet PDF文件第9页 
IDT7134SA/LA  
High-Speed 4K x 8 Dual-Port Static SRAM  
Military, Industrial and Commercial Temperature Ranges  
AC Electrical Characteristics Over the  
OperatingTemperatureandSupplyVoltage(3)  
7134X20  
7134X25  
Com'l, Ind  
& Military  
7134X35  
Com'l, Ind  
& Military  
Com'l Only  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
____  
____  
____  
t
RC  
AA  
ACE  
AOE  
OH  
LZ  
HZ  
PU  
PD  
Read Cycle Time  
20  
25  
35  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
t
Address Access Time  
Chip Enable Access Time  
20  
20  
25  
25  
35  
35  
____  
____  
____  
____  
____  
____  
t
t
Output Enable Access Time  
Output Hold from Address Change  
Output Low-Z Time(1,2)  
15  
15  
20  
____  
____  
____  
t
0
0
0
____  
____  
____  
t
0
0
0
Output High-Z Time(1,2)  
15  
15  
20  
____  
____  
____  
t
t
Chip Enable to Power Up Time(2)  
Chip Disable to Power Down Time(2)  
0
0
0
____  
____  
____  
____  
____  
____  
t
20  
25  
35  
ns  
2720 tbl 09a  
7134X45  
Com'l &  
Military  
7134X55  
Com'l, Ind  
& Military  
7134X70  
Com'l &  
Military  
Symbol  
READ CYCLE  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
____  
____  
____  
t
RC  
AA  
ACE  
AOE  
OH  
LZ  
HZ  
PU  
PD  
Read Cycle Time  
45  
55  
70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
____  
____  
____  
t
Address Access Time  
45  
45  
55  
55  
70  
70  
____  
____  
____  
____  
____  
____  
t
Chip Enable Access Time  
Output Enable Access Time  
Output Hold from Address Change  
Output Low-Z Time(1,2)  
t
25  
30  
40  
____  
____  
____  
t
0
0
0
____  
____  
____  
t
5
5
5
Output High-Z Time(1,2)  
20  
25  
30  
____  
____  
____  
t
t
Chip Enable to Power Up Time(2)  
Chip Disable to Power Down Time(2)  
0
0
0
____  
____  
____  
____  
____  
____  
t
45  
50  
50  
ns  
2720 tbl 09b  
NOTES:  
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).  
2. This parameter is guaranteed by device characterization, but is not production tested.  
3. 'X' in part number indicates power rating (SA or LA).  
6

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