Datasheet > 7133LA55PFI

7133LA55PFI

更新时间： 2023-01-02 23:40:58

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
16页	137K
描述
Dual-Port SRAM, 2KX16, 55ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

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7133LA55PFI 数据手册

IDT7133SA/LA,IDT7143SA/LA

High-Speed 2K x 16 Dual-Port RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾

ADDR"A" AND "B"

ADDRESSES MATCH

CE"A"

(2)

APS

CE"B"

BAC

tBDC

BUSY"B"

2746 drw 13

Timing Waveform of BUSY Arbitration Controlled by Addresses⁽¹⁾

tRC

tWC

ADDR "A"

ADDR "B"

BUSY "B"

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

(2)

tAPS

tBAA

tBDA

2746 drw 14

NOTES:

1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted

(IDT7133 only).

6.42

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型号	品牌	描述	获取价格	数据表
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