IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Functional Description
The IDT7133/43 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT7133/43 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Non-contention READ/WRITE conditions
are illustrated in Truth Table 1.
LEFT
RIGHT
R/W
R/W
R/W
R/W
IDT7133
MASTER
BUSY
BUSY
BUSY
BUSY
270Ω
270Ω
V
CC
VCC
R/W
R/W
IDT7143
SLAVE
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAMhaveaccessedthesamelocationatthesametime. Italsoallows
one of the two accesses to proceed and signals the other side that the
RAM is “busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
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BUSY
BUSY
Figure 4. Busy and chip enable routing for both width and depth expansion
with the IDT7133 (MASTER) and the IDT7143 (SLAVE).
Expanding the data bus width to 32 bits or more in a Dual-Port RAM
tions. In some cases it may be useful to logically OR the BUSY outputs systemimpliesthatseveralchipswillbeactiveatthesametime.Ifeach
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe chip includes a hardware arbitrator, and the addresses for each chip
event of an illegal or illogical operation. If the write inhibit function of arrive at the same time, it is possible that one will activate its BUSYL
BUSY logic is not desirable, the BUSY logic can be disabled by using while another activates its BUSYR signal. Both sides are now BUSY
the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely and the CPUs will await indefinitely for their port to become free.
as a write inhibit input pin. Normal operation can be programmed by
To avoid the “Busy Lock-Out” problem, IDT has developed a
tying theBUSY pins HIGH. If desired, unintended write operations can MASTER/SLAVEapproachwhereonlyonehardwarearbitrator, inthe
be prevented to a port by tying the BUSY pin for that port LOW. The MASTER, is used. The SLAVE has BUSY inputs which allow an
BUSY outputs on the IDT 7133 RAM are open drain and require pull- interface to the MASTER with no external components and with a
up resistors.
speed advantage over other systems.
WhenexpandingDual-PortRAMsinwidth, thewritingoftheSLAVE
RAMs must be delayed until after the BUSY input has settled.
Otherwise,theSLAVEchipmaybeginawritecycleduringacontention
situation. Conversely, the write pulse must extend a hold time past
BUSY to ensure that a write cycle takes place after the contention is
resolved.ThistimingisinherentinallDual-Portmemorysystemswhere
morethanonechipisactiveatthesametime.
The write pulse to the SLAVE should be delayed by the maximum
arbitration time of the MASTER. If, then, a contention occurs, the write
totheSLAVEwillbeinhibitedduetoBUSYfromtheMASTER.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7133/43 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT7133RAMtheBUSYpinisanoutputandontheIDT7143RAM,the
BUSY pin is an input (see Figure 3).
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