Datasheet > 70V9159L9PFG

70V9159L9PFG

更新时间： 2022-12-29 20:46:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	205K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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数据手册

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70V9159L9PFG 数据手册

IDT70V9169/59L

High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-Through or Pipelined Outputs)⁽¹⁾

CYC2

tCH2

tCL2

CLK

tSA

tHA

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁷⁾

An + 4

An + 2

An + 1

An + 3

tSAD tHAD

ADS

CNTEN

tSD tHD

Dn + 4

Dn + 1

Dn + 3

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

5655 drw 17

Timing Waveform of Counter Reset (Pipelined Outputs)⁽²⁾

CYC2

tCH2

tCL2

CLK

tSA tHA

ADDRESS⁽⁴⁾

An + 2

An + 1

INTERNAL⁽³⁾

ADDRESS

Ax⁽⁶⁾

An + 1

SW tHW

R/W

ADS

CNTEN

tSRST

tHRST

CNTRST

DATAIN

(5)

DATAOUT

COUNTER⁽⁶⁾

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS n

READ

ADDRESS n+1

READ

ADDRESS 1

NOTES:

1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.

CE0 = VIL; CE1 = VIH.

5655 drw 18

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR0 will be accessed. Extra cycles

are shown here simply for clarification.

7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.

The ‘An +1’ Address is written to during this cycle.

6.1442

1...11 12 131415 16

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