IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A15L
A
0R - A15R
I/O0R - I/O7R
CLK
I/O0L - I/O7L
CLK
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
ADS
CNTEN
CNTRST
FT/PIPE
L
ADS
CNTEN
CNTRST
FT/PIPE
R
L
R
L
R
NOTE:
1. A15X is a NC for IDT70V9079.
L
R
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
V
V
DD
SS
3750 tbl 01
Truth Table I—Read/Write and
EnableControl(1,2,3)
Mode
CLK
CE
1
R/
W
I/O0-7
High-Z
High-Z
DATAIN
OE
CE
H
X
0
↑
X
X
X
Deselected - Power Down
Deselected - Power Down
Write
↑
X
L
X
L
↑
X
L
H
↑
L
L
H
H
X
DATAOUT Read
High-Z Outputs Disabled
H
X
L
H
3750 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,3)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
CLK
↑
I/O(3)
DI/O (n) External Address Used
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
H
H
An + 1
An + 1
L(5)
H
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
↑
X
An + 1
X
H
H
D
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
3750 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6.432