Datasheet > 70V7519S166BFG8

70V7519S166BFG8

更新时间： 2024-02-01 13:26:10

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	756K
描述
HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

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70V7519S166BFG8 数据手册

IDT70V7519S

High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)^(1,6)

CYC2

tCH2

tCL2

CLK

tSA

tHA

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁵⁾

An + 1

An + 3

An + 4

An + 2

tSAD tHAD

ADS

SCN tHCN

CNTEN

SD tHD

Dn + 4

Dn + 1

Dn + 3

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

5618 drw 18

Timing Waveform of Counter Repeat for Flow Through Mode^(2,6,7)

tCYC2

CLK

tSA tHA

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An+2

An+1

An+2

An+1

An+2

tSAD tHAD

ADS

tSW tHW

R/W

tSCN tHCN

CNTEN

(4)

REPEAT

_SRPTtHRPT

tSD

tHD

DATAIN

tCD1

An+1

An+2

DATAOUT

ADVANCE

COUNTER

WRITE TO

An+2

ADVANCE

HOLD

REPEAT

READ LAST

ADS

ADDRESS

ADVANCE

COUNTER

READ

WRITE TO

ADS

ADDRESS

ADVANCE

COUNTER

READ

HOLD

COUNTER

READ

COUNTER

WRITE TO

An+1

COUNTER

WRITE TO

An+2

An+1

An+2

5618 drw 19

NOTES:

1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.

CE0, BEn = VIL; CE1 = VIH.

3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.

4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.

7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

6.42

1...15 16 171819 20 21 22

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与70V7519S166BFG8相关器件

型号	品牌	获取价格	描述	数据表
70V7519S166BFGI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7519S166BFGI8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7519S166BFI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V7519S166DR	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V7519S166DRG	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7519S166DRG8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7519S166DRGI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM
70V7519S166DRGI8	IDT	获取价格	Dual-Port SRAM, 256KX36, 3.6ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC,
70V7519S166DRI	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.
70V7519S200BC	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.

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