Datasheet > 70V7319S166BCG8

70V7319S166BCG8

更新时间： 2022-02-26 08:56:34

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	744K
描述
HIGH-SPEED 3.3V 256K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

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70V7319S166BCG8 数据手册

IDT70V7319S

High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

Chip Enables

CE0L

CE1L

CE0R, CE1R

R/W

BA0L - BA5L

0L - A11 L

I/O0L - I/O17L

CLK

PL/FT

ADS

CNTEN

REPEAT

R/W

BA0R - BA5R

0R - A11R

I/O0R - I/O17R

CLK

PL/FT

ADS

CNTEN

REPEAT

LB , UB

Read/Write Enable

Output Enable

Bank Address⁽⁴⁾

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat⁽³⁾

Byte Enables (9-bit bytes)

Power (I/O Bus) (3.3V or 2.5V)⁽¹⁾

NOTES:

1. VDD,OPTX,andVDDQXmustbesettoappropriateoperatinglevelspriortoapplyinginputs

ontheI/Osandcontrolsforthatport.

2. OPTXselectstheoperatingvoltagelevelsfortheI/Osandcontrolsonthatport.IfOPTXis

settoVIH(3.3V),thenthatport'sI/Osandcontrolswilloperateat3.3VlevelsandVDDQXmust

besuppliedat3.3V.IfOPTXissettoVIL(0V),thenthatport'sI/Osandaddresscontrolswill

operateat2.5VlevelsandVDDQXmustbesuppliedat2.5V.TheOPTpinsareindependent

ofoneanother—bothportscanoperateat3.3Vlevels,bothcanoperateat2.5Vlevels,oreither

canoperateat3.3Vwiththeotherat2.5V.

LBL

, UB

DDQL

DDQR

(1,2)

OPT

OPTR

Option for selecting VDDQX

Power (3.3V)⁽¹⁾

3. WhenREPEATXisasserted,thecounterwillresettothelastvalidaddressloadedviaADSX.

4. Accessesbytheportsintospecificbanksarecontrolledbythebankaddresspinsunder

theuser'sdirectcontrol:eachportcanaccessanybankofmemorywiththesharedarray

thatisnotcurrentlybeingaccessedbytheoppositeport(i.e.,BA0L -BA5L≠BA0R-BA5R).

Intheeventthatbothportstrytoaccessthesamebankatthesametime,neitheraccess

willbevalid,anddataatthetwospecificaddressestargetedbytheportswithinthatbankmay

becorrupted(inthecasethateitherorbothportsarewriting)ormayresultininvalidoutput

(inthecasethatbothportsaretryingtoread).

Ground (0V)

TDI

TDO

TCK

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

TMS

TRST

5629 tbl 01

6.42

1 2 345 6 7...22

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