IDT70V3569S
HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features:
◆
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V ( 150mV) power supply for
core
LVTTL- compatible, selectable 3.3V ( 150mV)/2.5V ( 125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
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– Commercial:4.2/5/6ns(max.)
– Industrial: 5ns (max)
Pipelined output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
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Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
GridArray
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
◆
Green parts availble, see ordering instructions
Functional Block Diagram
BE3L
BE3R
BE2R
BE1R
BE0R
BE2L
BE1L
BE0L
R/W
L
R/WR
B
B
B
B
B
B B B
W W W W W WW W
0
L
1
L
2
L
3
L
3
R
2
1
0
R
CE0L
R R
CE0R
CE1L
CE1R
OE
L
OER
Dout0-8_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
16K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Din_L
I/O0R - I/O35R
Din_R
,
CLK
L
CLKR
A
13L
A
A
13R
0R
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
ADDR_L
ADDR_R
CNTRST
ADS
CNTEN
L
CNTRST
ADS
CNTEN
R
R
L
L
R
4831 tbl 01
FEBRUARY 2018
1
DSC 4831/14
©2018 Integrated Device Technology, Inc.