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70V3569S5DRGI PDF预览

70V3569S5DRGI

更新时间: 2024-01-17 11:48:24
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
17页 211K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

70V3569S5DRGI 数据手册

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IDT70V3569S  
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM  
Industrial and Commercial Temperature Ranges  
Pin Configuration(1,2,3,4) (con't.)  
70V3569BC  
BC-256(5)  
256-Pin BGA  
Top View(6)  
12/12/01  
A1  
A2  
A3  
A6  
A7  
A8  
A9  
A11  
A12  
A13  
A14  
A4  
A5  
A10  
A15  
A16  
NC  
NC  
NC  
A
11L  
A
8L  
9L  
7L  
BE2L CE1L  
CNTEN  
L
A
5L  
4L  
6L  
A
2L  
A
0L  
NC  
NC  
OE  
L
NC  
NC  
B1  
B2  
B3  
B6  
B7  
B9  
CE0L  
B11  
B12  
B13  
B4  
B5  
B8  
B10  
B14  
B15  
B16  
I/O18L NC  
NC  
A
12L  
A
CNTRST  
L
A
A
1L  
NC  
NC  
BE3L  
R/W  
L
VDD I/O17L NC  
C1  
C5  
C6  
C2  
C3  
C4  
C7  
C8  
C9  
C10  
C11  
C12  
C13  
C16  
C14  
C15  
I/O18R  
A13L  
A
10L  
I/O19L  
VSS  
NC  
A
BE1L BE0L CLK  
L
ADS  
L
A
A
3L  
I/O16L  
OPT  
L
I/O17R  
D1  
D2  
D6  
DDQL  
D9  
D11  
D3  
D5  
DDQL  
D7  
DDQR  
D8  
D10  
D12  
D13  
D14  
D15  
D16  
D4  
I/O20R I/O19R  
V
VDDQL  
VDDQR  
I/O20L  
V
V
VDDQR  
VDDQL  
VDDQR  
VDD I/O15R I/O15L I/O16R  
V
DD  
E5  
E6  
E7  
E8  
E9  
E10  
E11  
E12  
E13  
E1  
E2  
E3  
E4  
DDQL  
E14  
E16  
E15  
V
DD  
V
DD  
SS  
SS  
V
SS  
V
SS  
SS  
SS  
SS  
V
SS  
VSS  
VDD  
VDD  
VDDQR  
I/O21R I/O21L I/O22L  
V
I/O13L  
I/O14R  
I/O14L  
F7  
F5  
F6  
F9  
F10  
F1  
F2  
F3  
F11  
F13  
F14  
F15  
F16  
F8  
F12  
F4  
V
SS  
I/O23L I/O22R I/O23R  
V
DD  
V
V
SS  
VSS  
I/O12R I/O13R I/O12L  
VDDQR  
VSS  
VDDQL  
V
VDD  
G1  
G2  
G3  
G5  
H5  
G4  
G6  
G8  
G9  
G14  
G15  
G16  
G7  
G10  
G12  
G13  
G11  
I/O24R  
V
SS  
SS  
SS  
I/O24L  
VDDQR  
V
V
V
SS  
I/O25L  
I/O10L I/O11L I/O11R  
H16  
V
SS  
VSS  
VSS  
VDDQL  
VSS  
H11  
H12  
H13  
H7  
H8  
H9  
H10  
H14  
H15  
H3  
I/O26R  
H4  
H6  
H1  
H2  
VSS  
VSS  
I/O10R  
VDDQL  
V
SS  
V
V
SS  
VSS  
I/O9R IO9L  
VDDQR  
V
VSS  
I/O26L I/O25R  
J1  
J2  
J3  
J4  
J5  
J6  
J7  
J8  
J9  
J13  
J10  
J11  
J12  
J14  
J15  
J16  
I/O27L  
V
I/O28R I/O27R  
VDDQL  
V
SS  
V
SS  
V
SS  
V
SS  
VDDQR  
VSS  
VSS  
VSS  
I/O8R  
I/O7R I/O8L  
K6  
K8  
K10  
K12  
K13  
K2  
K4  
K5  
L5  
K7  
K9  
K11  
K15  
K16  
K1  
K3  
K14  
V
SS  
V
SS  
VSS  
VSS  
VDDQR  
I/O29L  
VDDQL  
V
SS  
DD  
V
SS  
SS  
SS  
V
SS  
V
SS  
I/O6L I/O7L  
I/O29R  
I/O28L  
I/O6R  
L7  
L8  
L11  
L12  
L13  
L6  
L9  
L10  
L3  
L4  
L15  
L16  
L1  
L2  
L14  
V
V
SS  
V
SS  
VDD  
VDDQL  
I/O30R  
VDDQR  
V
V
SS  
V
SS  
VSS  
I/O4R I/O5R  
I/O30L I/O31R  
I/O5L  
M5  
M6  
M7  
M8  
M9  
M10  
M11  
M12  
M13  
M1 M2  
M3  
M4  
M16  
M14  
M15  
V
DD  
V
DD  
V
V
SS  
V
SS  
V
SS  
V
DD  
VDD  
VDDQL  
I/O32R I/O32L I/O31L  
VDDQR  
I/O4L  
I/O3R I/O3L  
N8  
N12  
N13  
N16  
N5  
N6  
DDQR  
N7  
DDQL  
N9  
N10  
N11  
N4  
N15  
N1  
N2  
N3  
N14  
VDDQL  
VDDQL  
I/O2R  
I/O1R  
VDD  
V
DD  
VDDQR  
V
V
VDDQR  
VDDQR  
VDDQL  
I/O33L I/O34R I/O33R  
I/O2L  
P1  
P2  
P3  
P4  
P5  
P7  
P8  
P9  
P10  
P11  
P12  
P14  
P15  
P16  
P6  
P13  
I/O35R I/O34L NC  
NC  
A13R  
A
7R BE1R BE0R CLK  
R
ADSR  
A6R  
I/O0L I/O0R I/O1L  
A10R  
A3R  
R5  
R6  
R7  
R8  
R9  
R10  
R11  
R16  
R1  
R2  
R3  
R4  
R12  
R13  
R14  
R15  
,
NC  
A
12R  
A
9R  
BE3R CE0R R/W  
R
CNTRST  
R
NC  
I/O35L NC  
NC  
NC  
A
4R  
A1R OPT  
R
NC  
T2  
T3  
T1  
T4  
T5  
T8  
T9  
T15  
T16  
T6  
T7  
T10  
T11  
T12  
T13  
T14  
NC  
NC  
NC  
NC  
NC  
BE2R CE1R  
NC  
NC  
A11R  
A8R  
OER  
CNTEN  
R
A5R  
A2R  
A0R  
4831 drw 02d  
NOTES:  
1. All VDD pins must be connected to 3.3V power supply.  
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is  
set to VIL (0V).  
,
3. All VSS pins must be connected to ground supply.  
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.  
5. This package code is used to reference the package diagram.  
6. This text does not indicate orientation of the actual part-marking.  
6.42  
3

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