Datasheet > 7008L55PFGB

7008L55PFGB

更新时间： 2023-06-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
20页	229K
描述
Multi-Port SRAM, 64KX8, 55ns, CMOS, PQFP100

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7008L55PFGB 数据手册

IDT7008S/L

High-Speed 64K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Chip Enable⁽¹⁾

Mode

CE0

Port Selected (TTL Active)

< 0.2V

>VCC -0.2V

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

Port Deselected (CMOS Inactive)

VIL

>VCC -0.2V

<0.2V

3198 tbl 02

NOTES:

1. Chip Enable references are shown above with the actual CE⁰and CE1 levels, CE is a reference only.

Truth Table II: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

(2 )

R/W

I/O0-7

Mode

SEM

High-Z

DATAIN

Deselected: Power-Down

Write to memory

DATAOUT Read memory

High-Z Outputs Disabled

3198 tbl 03

NOTES:

1. A0L – A15L ≠ A0R – A15R.

2. Refer to Chip Enable Truth Table.

Truth Table III: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

(2)

R/W

I/O0-7

Mode

SEM

↑

DATAOUT Read Semaphore Flag Data Out

DATAIN

Write I/O0 into Semaphore Flag

______

Not Allowed

3198 tbl 04

NOTES:

1. There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2.

2. Refer to Chip Enable Truth Table.

6.42

1 2 3 456 7 8...20

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