Datasheet > 7008L20GI

7008L20GI

更新时间： 2023-03-15 00:00:00

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
19页	158K
描述
Dual-Port SRAM, 64KX8, 20ns, CMOS, CPGA84, 1.120 X 1.120 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-84

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数据手册

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7008L20GI 数据手册

HIGH-SPEED

IDT7008S/L

64K x 8 DUAL-PORT

STATIC RAM

Features

◆

IDT7008 easily expands data bus width to 16 bits or

more using the Master/Slave select when cascading more

than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Commercial:15/20/25/35/55ns(max.)

– Industrial:20/55ns (max.)

– Military:25/35/55ns(max.)

Low-power operation

◆

– IDT7008S

Active:750mW(typ.)

Standby: 5mW (typ.)

– IDT7008L

◆

Active:750mW(typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

external logic

◆

Green parts available, see ordering information

FunctionalBlockDiagram

R/W

CE0L

CE1L

CE0R

OE_L

OE_R

I/O

Control

I/O

Control

I/O0-7L

I/O_0-7R

(1,2)

BUSY_L

(1,2)

BUSY_R

64Kx8

MEMORY

ARRAY

7008

15R

15L

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0L

CE_0R

R/W

OER

R/W

SEM

INTL

SEM

(2)

INT

M/S⁽¹⁾

3198 drw 01

NOTES:

1. BUSY is an input as a Slave (M/S = V^IL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

OCTOBER 2008

DSC 3198/9

12 3 4 5 6 7...19

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