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7007L20JG PDF预览

7007L20JG

更新时间: 2024-01-06 21:30:05
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 356K
描述
HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

7007L20JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCJ, PGA68,11X11针数:68
Reach Compliance Code:compliantECCN代码:3A991
HTS代码:8542.32.00.41风险等级:5.27
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-J68JESD-609代码:e3
长度:24.2062 mm内存密度:262144 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
湿度敏感等级:1功能数量:1
端口数量:2端子数量:68
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:PGA68,11X11
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:4.572 mm最大待机电流:0.005 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.275 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:24.2062 mmBase Number Matches:1

7007L20JG 数据手册

 浏览型号7007L20JG的Datasheet PDF文件第3页浏览型号7007L20JG的Datasheet PDF文件第4页浏览型号7007L20JG的Datasheet PDF文件第5页浏览型号7007L20JG的Datasheet PDF文件第7页浏览型号7007L20JG的Datasheet PDF文件第8页浏览型号7007L20JG的Datasheet PDF文件第9页 
IDT7007S/L  
High-Speed 32K x 8 Dual-Port Static RAM  
Military, Industrial and Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)  
7007S  
7007L  
Symbol  
|ILI  
|ILO  
Parameter  
Input Leakage Current(1)  
Output Leakage Current  
Output Low Voltage  
Test Conditions  
Min.  
Max.  
10  
Min.  
Max.  
Unit  
µA  
µA  
V
___  
___  
|
V
CC = 5.5V, VIN = 0V to VCC  
5
5
___  
___  
___  
___  
|
10  
CE = VIH, VOUT = 0V to VCC  
OL = 4mA  
OH = -4mA  
V
OL  
OH  
I
0.4  
0.4  
___  
___  
V
Output High Voltage  
I
2.4  
2.4  
V
2940 tbl 08  
NOTE:  
1. At Vcc < 2.0V, input leakages are undefined.  
DC Electrical Characteristics Over the Operating  
Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)  
7007X15  
7007X20  
Com'l & Ind  
7007X25  
Com'l, Ind  
& Military  
Com'l Only  
Symbol  
Parameter  
Test Condition  
Version  
COM'L  
Typ.(2)  
Max.  
Typ.(2)  
Max.  
Typ.(2)  
Max.  
Unit  
ICC  
Dynamic Operating  
Current  
(Both Ports Active)  
S
L
190  
190  
325  
285  
180  
180  
315  
275  
170  
170  
305  
265  
mA  
CE = VIL, Outputs Disabled  
SEM = VIH  
(3)  
f = fMAX  
___  
___  
___  
___  
___  
___  
MIL &  
IND  
S
L
170  
170  
345  
305  
180  
315  
I
SB1  
Standby Current  
(Both Ports - TTL Level  
Inputs)  
COM'L  
S
L
35  
35  
85  
60  
30  
30  
85  
60  
25  
25  
85  
60  
mA  
mA  
CE  
SEM  
f = fMAX  
L
= CE  
R
= VIH  
= VIH  
R
= SEM  
L
(3)  
___  
___  
___  
___  
___  
___  
MIL &  
IND  
S
L
25  
25  
100  
80  
30  
80  
(5)  
ISB2  
Standby Current  
(One Port - TTL Level  
Inputs)  
COM'L  
S
L
125  
125  
220  
190  
115  
115  
210  
180  
105  
105  
200  
170  
CE"A" = VIL and CE"B" = VIH  
Active Port Outputs Disabled,  
(3)  
f=fMAX  
___  
___  
___  
___  
___  
___  
MIL &  
IND  
S
L
105  
105  
230  
200  
SEMR = SEML = VIH  
115  
210  
I
SB3  
Full Standby Current  
(Both Ports - All CMOS  
Level Inputs)  
Both Ports CE  
CE > VCC - 0.2V  
IN > VCC - 0.2V or  
VIN < 0.2V, f = 0(4)  
SEM = SEM > VCC - 0.2V  
L
and  
COM'L  
S
L
1.0  
0.2  
15  
5
1.0  
0.2  
15  
5
1.0  
0.2  
15  
5
mA  
mA  
R
V
___  
___  
___  
___  
___  
___  
MIL &  
IND  
S
L
1.0  
0.2  
30  
10  
0.2  
10  
R
L
ISB4  
Full Standby Current  
(One Port - All CMOS  
Level Inputs)  
COM'L  
S
L
120  
120  
190  
160  
110  
110  
185  
160  
100  
100  
175  
160  
CE"A" < 0.2V and  
CE"B" > VCC - 0.2V(5)  
SEMR = SEML > VCC - 0.2V  
___  
___  
___  
___  
___  
___  
MIL &  
IND  
S
L
100  
100  
200  
175  
V
IN > VCC - 0.2V or VIN < 0.2V  
110  
185  
Active Port Outputs Disabled  
(3)  
f = fMAX  
2940 tbl 09  
NOTES:  
1. 'X' in part numbers indicates power rating (S or L)  
2. VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)  
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input  
levels of GND to 3V.  
4. f = 0 means no address or control lines change.  
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
6

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