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68901Q04

更新时间： 2024-02-20 22:05:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		时钟
页数	文件大小	规格书
33页	314K
描述
MULTI.FUNCTION PERIPHERAL

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技术参数
数据手册

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68901Q04 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	52
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.84	Is Samacsys：	N
地址总线宽度：	5	边界扫描：	NO
总线兼容性：	68000	最大时钟频率：	4 MHz
外部数据总线宽度：	8	JESD-30 代码：	S-PQCC-J52
长度：	19.1262 mm	I/O 线路数量：	8
端子数量：	52	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
座面最大高度：	4.572 mm	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
宽度：	19.1262 mm	Base Number Matches：	1

68901Q04 数据手册

MK68901

Figure 4 : Register Map.

Address Port N°.

Abbreviation

GPIP

AER

DDR

GENERAL PURPOSE I/O

ACTIVE EDGE REGISTER

DATA DIRECTION REGISTER

IERA

IERB

IPRA

IPRB

ISRA

ISRB

IMRA

IMRB

INTERRUPT ENABLE REGISTER A

INTERRUPT ENABLE REGISTER B

INTERRUPT PENDING REGISTER A

INTERRUPT PENDING REGISTER B

INTERRUPT IN-SERVICE REGISTER A

INTERRUPT IN-SERVICE REGISTER B

INTERRUPT MASK REGISTER A

INTERRUPT MASK REGISTER B

VECTOR REGISTER

TACR

TBCR

TCDCR

TADR

TBDR

TCDR

TDDR

TIMER A CONTROL REGISTER

TIMER B CONTROL REGISTER

TIMERS C AND D CONTROL REGISTER

TIMER A DATA REGISTER

TIMER B DATA REGISTER

TIMER C DATA REGISTER

TIMER D DATA REGISTER

SCR

UCR

RSR

TSR

UDR

SYNC CHARACTER REGISTER

USART CONTROL REGISTER

RECEIVER STATUS REGISTER

TRANSMITTER STATUS REGISTER

USART DATA REGISTER

INTERRUPTS

would then normally configure the AER before

enabling interrupts via IERA and IERB.

The General Purpose I/O-Interrupt Port (GPIP) pro-

vides eight I/O lines that may be operated either as

inputs oroutputs under software control. In addition,

each line may generate an interrupt in either a po-

sitive going edge or a negative going edge of the in-

put signal.

Note : Changing the edge bit, with the interrupt

enabled, may cause an interrupt on that channel.

The Data Direction Register (DDR) is used todefine

10-17 as inputs or as outputs on a bit by bit basis.

Writing a zero into a bit of the DDR causes the cor-

responding Interrupt-I/O pin to be a Hi-Z input. Wri-

ting a one into a bit of the DDR causes the cor-

responding pin to be configured as a push-pull out-

put. When data is written into the GPIP, those pins

defined as inputs will remain in the Hi-Z state while

those pins defined as outputs will assume the state

(high or low) of their corresponding bit in the GPIP.

When the GPIP is read, the data read will come di-

rectly fromthecorresponding bitofthe GPIPregister

for all pins defined as output, while the data read on

all pins defined as inputs will come from the input

buffers.

The GPIP has three associated registers. One al-

lows the programmer to specify the Active Edge for

each bitthat willtrigger an interrupt. Another register

specifies the Data Direction (input or output) asso-

ciated with each bit. The third register is the actual

data I/O register used to input or output data to the

port. These three registers are illstrated in figure 5.

The Active Edge Register (AER) allows each of the

General Purpose Interrupts to provide an interrupt

on either a 1-0 transition or a 0-1 transition. Writing

a zero to the appropriate bit of the AER causes the

associated input to produce an interrupt on the 1-0

transition. The edge bit is simply one input to an ex-

clusive-or gate, withthe other input coming from the

input buffer ant the output going to a 1-0 transition

detector. Thus, depending upon the state of the in-

put, writing the AER can cause an interrupt-produ-

cing transition, which will cause an interrupt on the

associated channel, if that channel is enabled. One

Each individual function in the MK68901 is provided

withaunique interrupt vectorthat is presented to the

systemduring the interrupt acknowledge cycle. The

interrupt vector returned during the interrupt ac-

knowledge cycle is shownin figure 6, while the vec-

tor register is shown in figure 7.

4/33

1 2 345 6 7...33

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与68901Q04相关器件

型号	品牌	描述	获取价格	数据表
68901Q05	STMICROELECTRONICS	MULTI.FUNCTION PERIPHERAL	获取价格
68902/BYCJC	ETC	Peripheral (Multifunction) Controller	获取价格
68902/BZAJC	ETC	Peripheral (Multifunction) Controller	获取价格
68905-002	AMPHENOL	Interconnection Device	获取价格
68905-101	AMPHENOL	Interconnection Device	获取价格
68905-102	AMPHENOL	Interconnection Device	获取价格

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