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651S

更新时间： 2023-12-20 18:46:27

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651S 数据手册

651S DATASHEET

Pin Assignment

ICLK

VDD

GND

VDD

GND

8 Pin (150 mil) SOIC

8-pin DFN

Pin Descriptions

Number

Name

Type

Pin Description

Clock input. Internal pull-up resistor.

ICLK

Input

Output Clock output 1.

Output Clock output 2.

Output Clock output 3.

Output Clock output 4.

GND

VDD

Power

Input

Connect to ground.

Connect +1.8V, +2.5V or +3.3V.

Output Enable. Tri-states outputs when low. Internal pull-up resistor.

External Components

A minimum number of external components are required for proper operation. A decoupling capacitor of 0.01F should be

connected between VDD on pin 7 and GND on pin 6, as close to the device as possible. A 33 series terminating resistor may

be used on each clock output if the trace is longer than 1 inch.

LOW SKEW 1 TO 4 CLOCK BUFFER

REVISION A 03/18/15

123 4 5 6 7...13

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