Datasheet > 635P3I3050M0000

635P3I3050M0000

更新时间： 2023-01-02 22:37:36

品牌	Logo	应用领域
西迪斯 - CTS		/
页数	文件大小	规格书
3页	224K
描述
LVPECL Output Clock Oscillator, 50MHz Nom,

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数据手册

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635P3I3050M0000 数据手册

Model 635

7.0mm x 5.0mm Low Jitter

LVPECL or LVDS Clock

ELECTRICAL CHARACTERISTICS

PARAMETER

Maximum Supply Voltage

Storage Temperature

Frequency Range

LVPECL

SYMBOL

V_CC

CONDITIONS

MIN

-0.5

-40

TYP

MAX

5.0

UNIT

T_STG

+100

°C

f_O

Δf/f_O

T_A

MHz

± ppm

°C

10.00

320

LVDS

80.00

320

Frequency Stability

All Inclusive, see Note 1.

1st year aging

20, 25, 50, 100

Operating Temperature

Commercial

-20

-40

+70

+85

2.63

3.47

Industrial

Supply Voltage

2.38

3.14

2.5

3.3

V_CC

± 5 %

Supply Current

LVPECL

I_CC

Maximum Load

LVDS

T_S

Application of V_CC

Start Up Time

Phase Jitter

tjrms

pjrms

Bandwidth 12 kHz - 20 MHz

0.3

2.6

0.7

Period Jitter RMS

Period Jitter Pk-Pk

Enable Function

Enable Input Voltage

Disable Input Voltage

Disable Time

Standby

V_IH

V_IL

0.7*V_CC

Pin 1 or 2 Logic '1', Output Enabled

Pin 1 or 2 Logic '0', Output Disabled

Pin 1 or 2 Logic '0' , Output Disabled

Pin 1 or 2 Logic '1', Output Enabled

0.3*V_CC

200

T_PLZ

Enable Time

LVPECL WAVEFORM

Output Load

R_L

Terminated to V_CC- 2.0V

@ V_CC- 1.3V

Ohms

Output Duty Cycle

Output Voltage Levels

Logic '1' Level

SYM

V_OH

V_OL

V_CC- 1.025

V_CC- 1.810

V_CC- 1.085

V_CC- 1.830

V_CC- 0.880

V_CC- 1.620

V_CC- 0.880

V_CC- 1.555

0.7

PECL Load, -20°C to +70°C

PECL Load, -40°C to +85°C

@ 20% - 80% Levels

Logic '0' Level

V_OH

Logic '1' Level

V_OL

Logic '0' Level

T_R, T_F

Rise and Fall Time

LVDS WAVEFORM

Output Load

0.3

R_L

Between Outputs

@ 1.25V

100

Ohms

Output Duty Cycle

Differential Output Voltage

Offset Voltage

SYM

V_OD

V_OS

R_L= 100 Ohms

LVDS Load

247

1.125

350

1.25

454

1.375

Output Voltage Levels

Logic '1' Level

V_OH

V_OL

LVDS Load

0.90

1.43

1.10

0.4

1.60

Logic '0' Level

LVDS Load

T_R, T_F

Rise and Fall Time

Notes:

@ 20% - 80% Levels

0.7

1. Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 1st year aging.

LVPECL/LVDS OUTPUT WAVEFORM

ENABLE TRUTH TABLE

PIN 1 or Pin 2

Logic ‘1’

PIN 4 & 5

Output

High Z

Open

Logic ‘0’

Document No. 008-0284-0

Page 2 - 3

Rev. E

123

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