5V49EE901PGGI

更新时间： 2024-02-13 01:15:32

品牌	Logo	应用领域
艾迪悌 - IDT		时钟发生器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
35页	728K
描述
EEPROM PROGRAMMABLE CLOCK GENERATOR

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5V49EE901PGGI 数据手册

IDT5V49EE901

EEPROM PROGRAMMABLE CLOCK GENERATOR

CLOCK SYNTHESIZER

Zero capacitor (Cz) = 196 pF + CZ* 217 pF

Spread Spectrum Generation (PLL3)

PLL3 support spread spectrum generation capability, which

users have the option of turning on and off. Spread

spectrum profile, frequency, and spread are fully

programmable (within limits). The technique is different from

that used in PLL0. The programmable spread spectrum

generation parameters are SS_D3[7:0], SSVCO[15:0],

SSENB, IP3[4:0] and RZ3[3:0] bits. These bits are in the

memory address range of 0x4C to 0x85 for PLL3. The

spread spectrum generation on PLL3 can be

Pole capacitor (Cp) = 15 pF

Charge pump (Ip) = 6 * (IP[0] + 2*IP[1]+4*IP[2]) uA

VCO gain (K^VCO) = 900 MHz/V * 2π

The following equations govern how the loop filter is set for

PLL3:

enabled/disabled using the SSENB bit. To enable spread

spectrum, set SSENB = '1'.

For Non-Spread Spectrum Operation:

(12.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))

Resistor(Rz)=

kOhms (Eq. 12)

kOhms (Eq. 13)

* RZ[0] +6*(1–RZ[0])

For Spread Enabled:

Spread spectrum is configured using SS_D3(spread

spectrum reference divide)

For Spread Spectrum Operation:

(62.5 + 12.5*(RZ[1] + 2*RZ[2] + 4*RZ[3]))

(Eq. 10)

SS_D3

Resistor(Rz)=

4 * F

* RZ[0] +6*(1–RZ[0])

MOD

and SSVCO (spread spectrum loop feedback counter).

Zero capacitor (Cz) = 250 pF

Pole capacitor (Cp) = 15 pF

VCO

( 1 + SS/400) + 5]

(Eq. 11)

SSVCO [0.5 *

MOD

For Non-Spread Spectrum Operation:

SS is the total Spread Spectrum amount (I.e. center spread

+0.5% has a total spread of 1.0% and down spread -0.5%

has a total spread of 0.5%.)

24* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))

Charge

A (Eq. 14)

pump (Ip)

3+(5* IP[3]) +(11* IP[4])

Loop Filter

For Spread Spectrum Operation:

The loop filter for each PLL can be programmed to optimize

the jitter performance. The low-pass frequency response of

the PLL is the mechanism that dictates the jitter transfer

characteristics. The loop bandwidth can be extracted from

the jitter transfer. A narrow loop bandwidth is good for jitter

attenuation while a wide loop bandwidth is best for low-jitter

frequency generation. The specific loop filter components

that can be programmed are the resistor via the RZ[3:0] bits,

zero capacitor via the CZ bit (for PLL0, PLL1 and PLL2), and

the charge pump current via the IP[2:0] bits (for PLL0, PLL1

and PLL2) or IP[3:0] (for PLL3).

12* (1+(2* IP[0]) +(4* IP[1]) +(8* IP[2]))

Charge

pump (Ip)

27+(5* IP[3]) +(11* IP[4])

VCO gain (K^VCO) = 900 MHz/V * 2π

The following equations govern how the loop filter is set for

PLL0 - PLL2:

Resistor (Rz) = (RZ[0] + 2* RZ[1]+4* RZ[2] + 8* RZ[3])* 4.0

kOhm

IDT® EEPROM PROGRAMMABLE CLOCK GENERATOR

IDT5V49EE901

REV J 022310

1...7 8 91011 12 13...35

中文翻译

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5V49EE901PGGI 替代型号

型号	品牌	替代类型	描述	数据表
5V49EE901PGGI	IDT	当前型号	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE901PGGI8	IDT	完全替代	EEPROM PROGRAMMABLE CLOCK GENERATOR

与5V49EE901PGGI相关器件

型号	品牌	获取价格	描述	数据表
5V49EE901PGGI8	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE902NLGI	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE902NLGI8	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE903NLGI	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE903NLGI8	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE903PGGI	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE903PGGI8	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE904NLGI	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V49EE904NLGI8	IDT	获取价格	EEPROM PROGRAMMABLE CLOCK GENERATOR
5V50009DCG	IDT	获取价格	SPREAD SPECTRUM CLOCK GENERATOR

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