Datasheet > 5V41235NLGI8

5V41235NLGI8

更新时间： 2022-02-26 09:59:21

品牌	Logo	应用领域
艾迪悌 - IDT		PC 输出元件
页数	文件大小	规格书
18页	317K
描述
2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

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5V41235NLGI8 数据手册

5V41235

2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

Applications Information

External Components

A minimum number of external components are required for

proper operation.

Output Structures

6*IREF

IREF

=2.3 mA

Decoupling Capacitors

Decoupling capacitors of 0.01F should be connected

between each VDD pin and the ground plane, as close to

the VDD pin as possible. Do not share ground vias between

components. Route power from power source through the

capacitor pad and then into ICS pin.

Crystal

See Output Termination

Sections - Pages 3 ~ 5

A 25 MHz fundamental mode parallel resonant crystal

should be used. This crystal must have less than 300 ppm

of error across temperature in order for the 5V41235 to meet

PCI Express specifications.

R_R475



General PCB Layout Recommendations

Crystal Capacitors

For optimum device performance and lowest output phase

noise, the following guidelines should be observed.

Crystal capacitors are connected from pins X1 to ground

and X2 to ground to optimize the accuracy of the output

frequency.

1. Each 0.01µF decoupling capacitor should be mounted on

the component side of the board as close to the VDD pin as

possible.

C = Crystal’s load capacitance in pF

Crystal Capacitors (pF) = (C - 7) * 2

2. No vias should be used between decoupling capacitor

and VDD pin.

For example, for a crystal with a 8pF load cap, each external

crystal cap would be 2pF [(8-7)*2=2].

3. The PCB trace to VDD pin should be kept as short as

possible, as should the PCB trace to the ground via.

Distance of the ferrite bead and bulk decoupling from the

device is less critical.

Current Source (Iref) Reference Resistor - R

If board target trace impedance (Z) is 50, then R = 475

(1%), providing IREF of 2.32 mA. The output current (I ) is

equal to 6*IREF.

4. An optimum layout is one with all components on the

same side of the board, minimizing vias through other signal

layers (any ferrite beads and bulk decoupling capacitors can

be mounted on the back). Other signal traces should be

routed away from the 5V41235.This includes signal traces

just underneath the device, or on layers adjacent to the

ground plane layer used by the device.

Output Termination

The PCI-Express differential clock outputs of the 5V41235

are open source drivers and require an external series

resistor and a resistor to ground. These resistor values and

their allowable locations are shown in detail in the

PCI-Express Layout Guidelines section.

The 5V41235 can also be configured for LVDS compatible

voltage levels. See the LVDS Compatible Layout

Guidelines section.

IDT® 2 OUTPUT PCIE GEN1/2/3 SYNTHESIZER

5V41235

MAY 5, 2017

1 2 345 6 7...18

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