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5PB1104PGGI8 PDF预览

5PB1104PGGI8

更新时间: 2024-01-14 21:02:04
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
21页 479K
描述
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family

5PB1104PGGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:1.59其他特性:IT ALSO OPERATES WITH 2.5V,3.3V
系列:5PB11输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.4 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:105 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):2.9 ns
Same Edge Skew-Max(tskwd):0.05 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):1.71 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3 mmBase Number Matches:1

5PB1104PGGI8 数据手册

 浏览型号5PB1104PGGI8的Datasheet PDF文件第4页浏览型号5PB1104PGGI8的Datasheet PDF文件第5页浏览型号5PB1104PGGI8的Datasheet PDF文件第6页浏览型号5PB1104PGGI8的Datasheet PDF文件第8页浏览型号5PB1104PGGI8的Datasheet PDF文件第9页浏览型号5PB1104PGGI8的Datasheet PDF文件第10页 
5PB11xx DATASHEET  
Parameter  
Start-up Time  
Symbol  
Conditions  
Min. Typ. Max. Units  
tSTART-UP Part start-up time for valid outputs after VDD ramp-up  
3
2.4  
2.7  
2.5  
0.05  
50  
ms  
ns  
Propagation Delay (5PB1102/04)  
Propagation Delay (5PB1106/08)  
Propagation Delay (5PB1110)  
Buffer Additive Phase Jitter, RMS  
Output to Output Skew (5PB1102/04)  
Output to Output Skew (5PB1106)  
Output to Output Skew (5PB1108/10)  
Device to Device Skew  
1.7  
1.7  
1.7  
2
2
2
Note 1  
ns  
ns  
156.25MHz, Integration Range: 12kHz-20MHz  
Rising edges at VDD/2, Note 2  
Rising edges at VDD/2, Note 2  
Rising edges at VDD/2, Note 2  
Rising edges at VDD/2  
ps  
35  
35  
45  
ps  
58  
ps  
65  
ps  
200  
3
ps  
Output Enable Time  
tEN  
CL < 5pF  
CL < 5pF  
cycles  
cycles  
Output Disable Time  
tDIS  
3
Notes:  
1. With rail to rail input clock  
2. Between any 2 outputs with equal loading.  
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.  
Phase Noise Plots  
Figure 2. 5PB11xx Output Phase Noise 70.9fs  
(12kHz to 20MHz)  
Figure 1. 5PB11xx Reference Phase Noise 58.9fs  
(12kHz to 20MHz)  
The phase noise plots above show the low additive jitter of the 5PB11xx high-performance buffer. With an integration range of  
12kHz to 20MHz, the reference input has about 58.9fs of RMS phase jitter while the output of 5PB11xx has about 70.9fs of RMS  
phase jitter. This results in a low additive phase jitter of only 39fs.  
Test Load and Circuit  
50ohms  
5 inche  
s
CL = 5pF  
MARCH 28, 2017  
7
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY  

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