5PB11xx DATASHEET
Parameter
Start-up Time
Symbol
Conditions
Min. Typ. Max. Units
tSTART-UP Part start-up time for valid outputs after VDD ramp-up
3
2.4
2.7
2.5
0.05
50
ms
ns
Propagation Delay (5PB1102/04)
Propagation Delay (5PB1106/08)
Propagation Delay (5PB1110)
Buffer Additive Phase Jitter, RMS
Output to Output Skew (5PB1102/04)
Output to Output Skew (5PB1106)
Output to Output Skew (5PB1108/10)
Device to Device Skew
1.7
1.7
1.7
2
2
2
Note 1
ns
ns
156.25MHz, Integration Range: 12kHz-20MHz
Rising edges at VDD/2, Note 2
Rising edges at VDD/2, Note 2
Rising edges at VDD/2, Note 2
Rising edges at VDD/2
ps
35
35
45
ps
58
ps
65
ps
200
3
ps
Output Enable Time
tEN
CL < 5pF
CL < 5pF
cycles
cycles
Output Disable Time
tDIS
3
Notes:
1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.
Phase Noise Plots
Figure 2. 5PB11xx Output Phase Noise 70.9fs
(12kHz to 20MHz)
Figure 1. 5PB11xx Reference Phase Noise 58.9fs
(12kHz to 20MHz)
The phase noise plots above show the low additive jitter of the 5PB11xx high-performance buffer. With an integration range of
12kHz to 20MHz, the reference input has about 58.9fs of RMS phase jitter while the output of 5PB11xx has about 70.9fs of RMS
phase jitter. This results in a low additive phase jitter of only 39fs.
Test Load and Circuit
50ohms
5 inche
s
CL = 5pF
MARCH 28, 2017
7
1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY