Datasheet > 5PB1102PGG

5PB1102PGG

更新时间： 2022-12-29 20:48:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	479K
描述
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family

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中文翻译

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数据手册

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5PB1102PGG 数据手册

5PB11xx DATASHEET

Pin Assignments for DFN/QFN Packages

CLKIN

5PB1102CMG

20 19 18 17 16

VDD

16 15

GND

VDD

GND

5PB1106CMG

5PB1110NDG

GND

VDD

CLKIN

VDD

5PB1104CMG

7 8

GND

VDD

7 8 9 10

GND

16 15

VDD

GND

5PB1108CMG

GND

VDD

7 8

Pin Descriptions for DFN/QFN Packages

LVCMOS

Clock Input

Clock Output

Enable

LVCMOS Clock Output

Supply Voltage

Ground

Device Number

CLKIN

Y0, Y1, . . . Y9

3, 8

VDD

GND

5PB1102CMG

5PB1104CMG

5PB1106CMG

5PB1108CMG

5PB1110NDG

3, 5, 7, 8

1, 4, 9, 11, 13, 14

1, 4, 6, 7, 9, 11, 13, 14

1, 4, 6, 8, 10, 11, 13, 15, 17, 18

3, 8, 12

3, 7, 12, 16

2, 5, 10

2, 5, 9, 14

Output Logic Table

Inputs

Output

CLKIN

After at least three cycles of input clock toggling. Output Enable function is asynchronous to eliminate any intermediate incorrect output clock cycles during transition which may cause

frequency peaking to the downstream device.

MARCH 28, 2017

1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY

1 234 5 6 7...21

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与5PB1102PGG相关器件

型号	品牌	获取价格	描述	数据表
5PB1102PGGI	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1102PGGI8	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1102PGGK	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1102PGGK8	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1104	RENESAS	获取价格	1.8 V to 3.3 V 1:4 LVCMOS High Performance Clock Buffer
5PB1104CMGI	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1104CMGI/	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1104CMGI/W	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1104CMGI8	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family
5PB1104CMGK	IDT	获取价格	1.8V to 3.3V LVCMOS High Performance Clock Buffer Family