Datasheet > 5PB1102CMGK

5PB1102CMGK

更新时间： 2022-12-29 20:48:07

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
21页	479K
描述
1.8V to 3.3V LVCMOS High Performance Clock Buffer Family

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数据手册

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5PB1102CMGK 数据手册

5PB11xx DATASHEET

Parameter

Start-up Time

Symbol

Conditions

Min. Typ. Max. Units

t_START-UPPart start-up time for valid outputs after VDD ramp-up

2.4

2.7

2.5

0.05

Propagation Delay (5PB1102/04)

Propagation Delay (5PB1106/08)

Propagation Delay (5PB1110)

Buffer Additive Phase Jitter, RMS

Output to Output Skew (5PB1102/04)

Output to Output Skew (5PB1106)

Output to Output Skew (5PB1108/10)

Device to Device Skew

1.7

Note 1

156.25MHz, Integration Range: 12kHz-20MHz

Rising edges at VDD/2, Note 2

Rising edges at VDD/2

200

Output Enable Time

t_EN

C_L< 5pF

cycles

Output Disable Time

t_DIS

Notes:

1. With rail to rail input clock

2. Between any 2 outputs with equal loading.

3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators.

Phase Noise Plots

Figure 2. 5PB11xx Output Phase Noise 70.9fs

(12kHz to 20MHz)

Figure 1. 5PB11xx Reference Phase Noise 58.9fs

(12kHz to 20MHz)

The phase noise plots above show the low additive jitter of the 5PB11xx high-performance buffer. With an integration range of

12kHz to 20MHz, the reference input has about 58.9fs of RMS phase jitter while the output of 5PB11xx has about 70.9fs of RMS

phase jitter. This results in a low additive phase jitter of only 39fs.

Test Load and Circuit

50ohms

5 inche

CL = 5pF

MARCH 28, 2017

1.8V TO 3.3V LVCMOS HIGH PERFORMANCE CLOCK BUFFER FAMILY

1...4 5 678 9 10...21

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