Datasheet > 5P35023

5P35023

更新时间： 2023-12-20 18:46:33

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
45页	1176K
描述
VersaClock? 3S Programmable Clock Generator

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5P35023 数据手册

5P35023 Datasheet

Block Diagram

DIV1/REF

DIV3

VDDDIFF2

OSC

DIFF2

DIFF2B

MUX

DIV1

DIV2

MUX

CLKINB/X1

VDDDIFF1

PLL1

PLL2

DIV1/REF

DIV3

CLKIN/X2

DIFF1

DIFF1B

DIV2

OE3

Power

VBAT

MUX

DIV3

DIV4

DIV4/REF

32K

MUX

SE3

VDDSE3

Monitor

VDD33

POR

DIV4/REF

DIV5

OE2

SE2

VDDSE2

32K

VDDA

MUX

PLL3

DIV5

DIV4/REF

OE1

SE1

Calibration

DIV5

32K

VSS

VDDSE1

32.768K

DCO

REF

SCL_DFC1

Overshoot Reduction

(ORT)

I2C Engine

Dynamic Frequency Control Logic (DFC)

SDA_DFC0

OTP memory (1 configuration)

Proactive Power Saving Logic (PPS)

Timer

Pin Assignments

Figure 1. Pin Assignments for 4 x 4 mm 24-VFQFPN Package – Top View

VDDA

SDA_DFCO

DIFF1

DIFF1B

VDDDIFF1

OE1

SEL_DFC/SCL_DFC1

CLKIN/X2

5P35023

CLKINB/X1

SE1

VBAT

VDDSE1

24-VFQFPN

November 22, 2023

1 234 5 6 7...45

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