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5M2210ZF324A5N PDF预览

5M2210ZF324A5N

更新时间: 2024-01-24 09:08:46
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
72页 1170K
描述
Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324,

5M2210ZF324A5N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA324,18X18,40Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.57
其他特性:YES系统内可编程:YES
JESD-30 代码:S-PBGA-B324JTAG BST:YES
宏单元数:1700端子数量:324
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA324,18X18,40封装形状:SQUARE
封装形式:GRID ARRAY电源:1.8,1.2/3.3 V
可编程逻辑类型:FLASH PLD传播延迟:11.2 ns
认证状态:Not Qualified筛选级别:AEC-Q100
子类别:Programmable Logic Devices表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOMBase Number Matches:1

5M2210ZF324A5N 数据手册

 浏览型号5M2210ZF324A5N的Datasheet PDF文件第1页浏览型号5M2210ZF324A5N的Datasheet PDF文件第2页浏览型号5M2210ZF324A5N的Datasheet PDF文件第3页浏览型号5M2210ZF324A5N的Datasheet PDF文件第5页浏览型号5M2210ZF324A5N的Datasheet PDF文件第6页浏览型号5M2210ZF324A5N的Datasheet PDF文件第7页 
1–2  
Chapter 1: MAX V Device Family Overview  
Feature Summary  
I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision  
2.2 for 3.3-V operation  
Hot-socket compliant  
Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990  
Table 1–1 lists the MAX V family features.  
Table 1–1. MAX V Family Features  
Feature  
5M40Z  
40  
5M80Z  
80  
5M160Z  
160  
128  
8,192  
4
5M240Z  
240  
192  
8,192  
4
5M570Z  
570  
440  
8,192  
4
5M1270Z 5M2210Z  
LEs  
1,270  
980  
8,192  
4
2,210  
1,700  
8,192  
4
Typical Equivalent Macrocells  
User Flash Memory Size (bits)  
Global Clocks  
32  
64  
8,192  
4
8,192  
4
Internal Oscillator  
Maximum User I/O pins  
tPD1 (ns) (1)  
1
1
1
1
1
1
1
54  
79  
79  
114  
7.5  
159  
9.0  
271  
6.2  
271  
7.0  
7.5  
152  
2.3  
6.5  
7.5  
152  
2.3  
6.5  
7.5  
fCNT (MHz) (2)  
152  
2.3  
152  
2.3  
152  
2.2  
304  
1.2  
304  
1.2  
t
SU (ns)  
tCO (ns)  
6.5  
6.5  
6.7  
4.6  
4.6  
Notes to Table 1–1:  
(1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic  
implemented in a single LUT and LAB that is adjacent to the output pin.  
(2) The maximum global clock frequency, fCNT, is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster  
than this number.  
MAX V devices accept 1.8 V on their VCCINTpins. The 1.8-V VCCINT external supply  
powers the device core directly. MAX V devices operate internally at 1.8 V. The  
supported MultiVolt I/O interface voltage levels (VCCIO) are 1.2 V, 1.5 V, 1.8 V, 2.5 V,  
and 3.3 V.  
MAX V devices are available in two speed grades: –4 and –5, with –4 being the fastest.  
For commercial applications, speed grades –C4 and –C5 are available. For industrial  
and automotive applications, speed grade –I5 and –A5 are available, respectively.  
These speed grades represent the overall relative performance, not any specific timing  
parameter.  
f For propagation delay timing numbers within each speed grade and density, refer to  
the DC and Switching Characteristics for MAX V Devices chapter.  
MAX V devices are available in space-saving FineLine BGA (FBGA), Micro FineLine  
BGA (MBGA), plastic enhanced quad flat pack (EQFP), and thin quad flat pack  
(TQFP) packages (refer to Table 1–2 and Table 1–3). MAX V devices support vertical  
migration within the same package (for example, you can migrate between the  
5M570Z, 5M1270Z, and 5M2210Z devices in the 256-pin FineLine BGA package).  
Vertical migration means that you can migrate to devices whose dedicated pins and  
JTAG pins are the same and power pins are subsets or supersets for a given package  
across device densities. The largest density in any package has the highest number of  
power pins; you must lay out for the largest planned density in a package to provide  
MAX V Device Handbook  
May 2011 Altera Corporation  

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