Datasheet > 5M2210ZF324A5N

5M2210ZF324A5N

更新时间： 2024-01-11 20:27:41

品牌	Logo	应用领域
英特尔 - INTEL		可编程逻辑
页数	文件大小	规格书
72页	1170K
描述
Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324,

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5M2210ZF324A5N 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA324,18X18,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.57
其他特性：	YES	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B324	JTAG BST：	YES
宏单元数：	1700	端子数量：	324
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA324,18X18,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	1.8,1.2/3.3 V
可编程逻辑类型：	FLASH PLD	传播延迟：	11.2 ns
认证状态：	Not Qualified	筛选级别：	AEC-Q100
子类别：	Programmable Logic Devices	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

5M2210ZF324A5N 数据手册

2. MAX V Architecture

MV51002-1.0

This chapter describes the architecture of the MAX^®V device and contains the

following sections:

■

“Functional Description” on page 2–1

“Logic Array Blocks” on page 2–4

“Logic Elements” on page 2–8

“MultiTrack Interconnect” on page 2–14

“Global Signals” on page 2–19

“User Flash Memory Block” on page 2–21

“Internal Oscillator” on page 2–22

“Core Voltage” on page 2–25

“I/O Structure” on page 2–26

Functional Description

MAX V devices contain a two-dimensional row- and column-based architecture to

implement custom logic. Row and column interconnects provide signal interconnects

between the logic array blocks (LABs).

Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of

logic that provides efficient implementation of user logic functions. LABs are grouped

into rows and columns across the device. The MultiTrack interconnect provides fast

granular timing delays between LABs. The fast routing between LEs provides

minimum timing delay for added levels of logic versus globally routed interconnect

structures.

The I/O elements (IOEs) located after the LAB rows and columns around the

periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional

I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs

and various single-ended standards, such as 33-MHz, 32-bit PCI™, and LVTTL.

MAX V devices provide a global clock network. The global clock network consists of

four global clock lines that drive throughout the entire device, providing clocks for all

resources within the device. You can also use the global clock lines for control signals

such as clear, preset, or output enable.

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

December 2010

1...4 5 678 9 10...72

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与5M2210ZF324A5N相关器件

型号	品牌	描述	获取价格	数据表
5M2210ZF324C4N	ALTERA	Flash PLD, 9.1ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF324C5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF324I5	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, FBGA-324	获取价格
5M2210ZF324I5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF64A4N	ALTERA	MAX V Device Handbook	获取价格
5M2210ZF64C5N	ALTERA	MAX V Device Handbook	获取价格

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