Datasheet > 5M2210ZF324A5N

5M2210ZF324A5N

更新时间： 2024-02-27 00:53:15

品牌	Logo	应用领域
英特尔 - INTEL		可编程逻辑
页数	文件大小	规格书
72页	1170K
描述
Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324,

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5M2210ZF324A5N 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	BGA, BGA324,18X18,40	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.57
其他特性：	YES	系统内可编程：	YES
JESD-30 代码：	S-PBGA-B324	JTAG BST：	YES
宏单元数：	1700	端子数量：	324
最高工作温度：	105 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA324,18X18,40	封装形状：	SQUARE
封装形式：	GRID ARRAY	电源：	1.8,1.2/3.3 V
可编程逻辑类型：	FLASH PLD	传播延迟：	11.2 ns
认证状态：	Not Qualified	筛选级别：	AEC-Q100
子类别：	Programmable Logic Devices	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

5M2210ZF324A5N 数据手册

1. MAX V Device Family Overview

MV51001-1.2

The MAX^®V family of low cost and low power CPLDs offer more density and I/Os

per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements

(LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide

programmable solutions for applications such as I/O expansion, bus and protocol

bridging, power monitoring and control, FPGA configuration, and analog IC

interface.

MAX V devices feature on-chip flash storage, internal oscillator, and memory

functionality. With up to 50% lower total power versus other CPLDs and requiring as

few as one power supply, MAX V CPLDs can help you meet your low power design

requirement.

This chapter contains the following sections:

■

“Feature Summary” on page 1–1

“Integrated Software Platform” on page 1–3

“Device Pin-Outs” on page 1–3

“Ordering Information” on page 1–4

Feature Summary

The following list summarizes the MAX V device family features:

■

Low-cost, low-power, and non-volatile CPLD architecture

Instant-on (0.5 ms or less) configuration time

Standby current as low as 25 µA and fast power-down/reset operation

Fast propagation delay and clock-to-output times

Internal oscillator

Emulated RSDS output support with a data rate of up to 200 Mbps

Emulated LVDS output support with a data rate of up to 304 Mbps

Four global clocks with two clocks available per logic array block (LAB)

User flash memory block up to 8 Kbits for non-volatile storage with up to 1000

read/write cycles

■

Single 1.8-V external supply for device core

MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels

Bus-friendly architecture including programmable slew rate, drive strength,

bus-hold, and programmable pull-up resistors

■

Schmitt triggers enabling noise tolerant inputs (programmable per pin)

and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at

www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but

reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any

information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device

specifications before relying on any published information and before placing orders for products or services.

MAX V Device Handbook

May 2011

1 234 5 6 7...72

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与5M2210ZF324A5N相关器件

型号	品牌	描述	获取价格	数据表
5M2210ZF324C4N	ALTERA	Flash PLD, 9.1ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF324C5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF324I5	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, FBGA-324	获取价格
5M2210ZF324I5N	ALTERA	Flash PLD, 11.2ns, 1700-Cell, CMOS, PBGA324, 19 X 19 MM, 1 MM PITCH, LEAD FREE, FBGA-324	获取价格
5M2210ZF64A4N	ALTERA	MAX V Device Handbook	获取价格
5M2210ZF64C5N	ALTERA	MAX V Device Handbook	获取价格

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