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5CEFA7U19A7N PDF预览

5CEFA7U19A7N

更新时间: 2024-02-26 22:54:42
品牌 Logo 应用领域
英特尔 - INTEL 可编程逻辑
页数 文件大小 规格书
95页 1359K
描述
Field Programmable Gate Array, 150000-Cell, CMOS, PBGA484, ROHS COMPLIANT, UBGA-484

5CEFA7U19A7N 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:ROHS COMPLIANT, UBGA-484Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.6
JESD-30 代码:S-PBGA-B484长度:19 mm
输入次数:240逻辑单元数量:150000
输出次数:240端子数量:484
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:FBGA
封装等效代码:BGA484,22X22,32封装形状:SQUARE
封装形式:GRID ARRAY, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.1,1.2/3.3,2.5 V可编程逻辑类型:FIELD PROGRAMMABLE GATE ARRAY
认证状态:Not Qualified座面最大高度:1.9 mm
子类别:Field Programmable Gate Arrays最大供电电压:1.13 V
最小供电电压:1.07 V标称供电电压:1.1 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19 mm
Base Number Matches:1

5CEFA7U19A7N 数据手册

 浏览型号5CEFA7U19A7N的Datasheet PDF文件第88页浏览型号5CEFA7U19A7N的Datasheet PDF文件第89页浏览型号5CEFA7U19A7N的Datasheet PDF文件第90页浏览型号5CEFA7U19A7N的Datasheet PDF文件第92页浏览型号5CEFA7U19A7N的Datasheet PDF文件第93页浏览型号5CEFA7U19A7N的Datasheet PDF文件第94页 
CV-51002  
2015.12.04  
91  
Document Revision History  
Date  
Version  
Changes  
January 2015  
2015.01.23  
• Updated the transceiver specification for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the  
following tables:  
• Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices  
• Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices  
• Transceiver Compliance Specification for All Supported Protocol for Cyclone V Devices  
• Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that  
VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6  
devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables:  
• Absolute Maximum Ratings for Cyclone V Devices  
• HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices  
• Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the  
maximum achievable frequency for general purpose I/O standards.  
• Updated the conditions for transceiver reference clock rise time and fall time: Measure at 60 mV of  
differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK  
phase noise specification.  
• Updated fVCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL  
specifications table.  
• Updated the description in Periphery Performance Specifications to mention that proper timing closure is  
required in design.  
• Added the following notes in the High-Speed I/O Specifications for Cyclone V Devices table:  
• The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true  
LVDS output buffer types on all I/O banks.  
• The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using  
true LVDS output buffer types on all I/O banks.  
• Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed  
grade.  
• Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and  
1,850 MHz (for –C6 speed grade).  
• Changed the symbol for HPS PLL input jitter divide value from NR to N.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  

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