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5CEBA2U15C7N PDF预览

5CEBA2U15C7N

更新时间： 2024-01-15 15:40:34
品牌 Logo 应用领域
阿尔特拉 - ALTERA LTE栅可编程逻辑
页数 文件大小 规格书
37页 353K
描述
Field Programmable Gate Array, PBGA324, ROHS COMPLIANT, UBGA-324

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5CEBA2U15C7N 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：LFBGA, BGA324,18X18,32Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.57
JESD-30 代码：S-PBGA-B324长度：15 mm
输入次数：176逻辑单元数量：25000
输出次数：176端子数量：324
最高工作温度：85 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA324,18X18,32封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.1,1.2/3.3,2.5 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.5 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.13 V
最小供电电压：1.07 V标称供电电压：1.1 V
表面贴装：YES技术：CMOS
温度等级：OTHER端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：15 mm
Base Number Matches：1

5CEBA2U15C7N 数据手册

 浏览型号5CEBA2U15C7N的Datasheet PDF文件第2页浏览型号5CEBA2U15C7N的Datasheet PDF文件第3页浏览型号5CEBA2U15C7N的Datasheet PDF文件第4页浏览型号5CEBA2U15C7N的Datasheet PDF文件第6页浏览型号5CEBA2U15C7N的Datasheet PDF文件第7页浏览型号5CEBA2U15C7N的Datasheet PDF文件第8页 
Cyclone V Device Overview  
CV-51001 | 2018.05.07  
Feature  
Description  
•
•
•
HPS–FPGA bridges—include the FPGA-to-HPS, HPS-to-FPGA, and lightweight HPS-to-FPGA  
bridges that allow the FPGA fabric to issue transactions to slaves in the HPS, and vice versa  
FPGA-to-HPS SDRAM controller subsystem—provides a configurable interface to the multiport  
front end (MPFE) of the HPS SDRAM controller  
Arm CoreSight™ JTAG debug access port, trace port, and on-chip trace storage  
Configuration  
•
•
•
•
•
Tamper protection—comprehensive design protection to protect your valuable IP investments  
Enhanced advanced encryption standard (AES) design security features  
CvP  
Dynamic reconfiguration of the FPGA  
Active serial (AS) x1 and x4, passive serial (PS), JTAG, and fast passive parallel (FPP) x8 and  
x16 configuration options  
•
•
Internal scrubbing (2)  
Partial reconfiguration (3)  
Cyclone V Device Variants and Packages  
Table 3.  
Device Variants for the Cyclone V Device Family  
Variant  
Cyclone V E  
Description  
Optimized for the lowest system cost and power requirement for a wide spectrum of general logic  
and DSP applications  
Cyclone V GX  
Cyclone V GT  
Optimized for the lowest cost and power requirement for 614 Mbps to 3.125 Gbps transceiver  
applications  
The FPGA industry’s lowest cost and lowest power requirement for 6.144 Gbps transceiver  
applications  
Cyclone V SE  
Cyclone V SX  
Cyclone V ST  
SoC with integrated Arm-based HPS  
SoC with integrated Arm-based HPS and 3.125 Gbps transceivers  
SoC with integrated Arm-based HPS and 6.144 Gbps transceivers  
Cyclone V E  
This section provides the available options, maximum resource counts, and package  
plan for the Cyclone V E devices.  
The information in this section is correct at the time of publication. For the latest  
information and to get more details, refer to the Product Selector Guide.  
Related Information  
Product Selector Guide  
Provides the latest information about Intel products.  
(2)  
(3)  
The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with  
the "SC" suffix in the part number. For device availability and ordering, contact your local Intel  
sales representatives.  
The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with  
the "SC" suffix in the part number. For device availability and ordering, contact your local  
Intel® sales representatives.  
Cyclone V Device Overview  
5
 
 
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