Datasheet > 5AGXMB7H4F35C5N

5AGXMB7H4F35C5N

更新时间： 2023-08-15 00:00:00

品牌	Logo	应用领域
英特尔 - INTEL		栅
页数	文件大小	规格书
122页	2542K
描述
Field Programmable Gate Array, 622MHz, PBGA1152, ROHS COMPLIANT, FBGA-1152

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Page 46

I/O Timing

Table 53. Remote System Upgrade Circuitry Timing Specifications (Part 2 of 2)

Parameter

Minimum

Maximum

Unit

(3)

t_{RU_nRSTIMER}

250

—

Notes to Table 53:

(1) This clock is user-supplied to the remote system upgrade circuitry. If you are using the ALTREMOTE_UPDATE

megafunction, the clock user-supplied to the ALTREMOTE_UPDATE megafunction must meet this specification.

(2) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. refer to the “Remote System Upgrade State Machine” section in the Configuration,

Design Security, and Remote System Upgrades in Arria V Devices chapter.

(3) This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high for the

minimum timing specification. For more information, refer to the “User Watchdog Timer” section in the

Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.

User Watchdog Internal Oscillator Frequency Specification

Table 54 lists the frequency specifications for the user watchdog internal oscillator.

Table 54. User Watchdog Internal Oscillator Frequency Specifications

Minimum

Typical

Maximum

Unit

5.3

7.9

12.5

MHz

I/O Timing

Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the

Quartus II Timing Analyzer.

Excel-based I/O timing provides pin timing performance for each device density and

speed grade. The data is typically used prior to designing the FPGA to get an estimate

of the timing budget as part of the link timing analysis.

The Quartus II Timing Analyzer provides a more accurate and precise I/O timing

data based on the specifics of the design after you complete place-and-route.

You can download the Excel-based I/O Timing spreadsheet from the Arria V Devices

Documentation webpage.

Programmable IOE Delay

Table 55 lists the Arria V GZ IOE programmable delay settings.

Table 55. IOE Programmable Delay for Arria V GZ Devices (Part 1 of 2)

Fast Model

Available

Slow Model

(1)

(2)

Parameter

Min Offset

Unit

Settings

Industrial

0.464

Commercial

0.493

I3L

0.924

0.459

2.992

0.924

1.011

0.503

3.192

1.011

0.921

0.456

3.047

0.920

0.921

1.006

0.500

3.257

1.006

0.230

0.244

1.587

1.699

0.464

0.492

0.464

0.493

Arria V GZ Device Datasheet

December 2013 Altera Corporation

1...113 114 115116117 118 119...122

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