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5962F9671601MEX

更新时间： 2022-12-01 22:12:29
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
26页 206K
描述
ACT SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, CDIP16, CERAMIC, DIP-16

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5962F9671601MEX 数据手册

 浏览型号5962F9671601MEX的Datasheet PDF文件第6页浏览型号5962F9671601MEX的Datasheet PDF文件第7页浏览型号5962F9671601MEX的Datasheet PDF文件第8页浏览型号5962F9671601MEX的Datasheet PDF文件第10页浏览型号5962F9671601MEX的Datasheet PDF文件第11页浏览型号5962F9671601MEX的Datasheet PDF文件第12页 
TABLE IA. Electrical performance characteristics - Continued.  
Test  
Symbol  
Test conditions 1/  
-55°C ≤ TC ≤ +125°C  
Device  
type  
VCC  
Group A  
subgroups  
Limits 2/  
Unit  
ns  
Min  
Max  
unless otherwise specified  
Output transition  
time  
tTHL  
,
CL = 50 pF  
RL = 500Ω  
See figure 4  
All  
4.5 V  
9
1.0  
1.0  
11.0  
12.0  
tTLH  
9/ 10/  
10, 11  
M, D, P, L, R, F  
4/  
All  
All  
9
1.0  
12.0  
Maximum clock  
frequency  
fMAX  
10/  
CL = 50 pF  
RL = 500Ω  
See figure 4  
4.5 V  
4.5 V  
4.5 V  
4.5 V  
9
10, 11  
9
50.0  
35.0  
10.0  
10.0  
10.0  
10.0  
10.0  
10.0  
MHz  
ns  
Setup time, high or  
low, Pn to CP  
ts1  
10/  
All  
All  
All  
10, 11  
9
Setup time, high or  
low, PE or TE to  
CP  
ts2  
10/  
ns  
10, 11  
9
Setup time, high or  
low, SPE to CP  
ts3  
10/  
ns  
10, 11  
Hold time, high or  
low, Pn to CP  
th1  
10/  
All  
All  
4.5 V  
4.5 V  
9
0.0  
0.0  
0.0  
0.0  
ns  
ns  
10, 11  
9
Hold time, high or  
low, PE or TE to  
CP  
th2  
10/  
10, 11  
Hold time, high or  
low, SPE to CP  
th3  
10/  
All  
All  
All  
All  
4.5 V  
4.5 V  
4.5 V  
4.5 V  
9
10, 11  
9
0.0  
0.0  
ns  
ns  
ns  
ns  
CP pulse width,  
high or low  
tw1  
10/  
5.0  
10, 11  
9
5.0  
MR pulse width,  
low  
tw2  
10/  
5.0  
10, 11  
9
5.0  
Recovery time, MR  
to CP  
tREC  
10/  
10.0  
10.0  
10, 11  
See footnotes on next sheet.  
SIZE  
STANDARD  
5962-96716  
A
MICROCIRCUIT DRAWING  
DEFENSE SUPPLY CENTER COLUMBUS  
COLUMBUS, OHIO 43218-3990  
REVISION LEVEL  
D
SHEET  
9
DSCC FORM 2234  
APR 97  
1...6789101112...26

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