Datasheet > 5962-JM38510/55501BZXC

5962-JM38510/55501BZXC

更新时间： 2022-11-24 21:17:35

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页数	文件大小	规格书
52页	1271K
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RTI Remote Terminal Interface

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Shared

Memory

CONTROL

Host

Computer

RTI

UT1553B

DATA(15:0)

ADDR(10:0)

DMA

CONTROLLER

Figure 2. Direct Memory Access Conﬁguration

The host microprocessor gains access to the RTI internal

registers by controlling input pins CS, CTRL, ADDR IN

(10:0), and RD/WR. During message processing the host

microprocessorshouldlimitaccesstoRTIinternalregisters.

The host microprocessor gains access to the RTI internal

registers by controlling input pins CS, CTRL, ADDR IN

(10:0), and RD/WR. During message processing the host

microprocessorshouldlimitaccesstoRTIinternalregisters.

The host should not assert CS while the RTI is performing

a memory access.

1.1.2 Transparent Memory Access

Conﬁgured in the transparent memory mode the host

microprocessor accesses shared memory through the RTI.

Arbitration for access to the bus is performed as discussed

in section 1.1.1 of this document.

1.2 Internal Register Description

The RTI uses three internal registers to allow the host to

control the RTI operation and monitor its status. The host

uses the following inputs Control (CTRL), Chip Select

(CS), Read/Write (RD/WR), and ADDR IN (0) to read the

16-bitSystemRegisterorwritetothe8-bitControlRegister.

The Control Register toggles bits in the MIL-STD-1553B

status word, enables biphase inputs, selects terminal active

ﬂag, and puts the part in self-test. The System Register

supplies operational status of the UT1553B RTI to the host.

The Last Command Register saves the command word for

a Transmit Last Command mode code, along with

operational status from the System Register.

When granted access to memory, the RTI asserts memory

control signals ADDR OUT(10:0), RCS, and RRD/RWR.

For host-controlled memory accesses the RAM memory

address from the host is propagated from theAddress In bus

ADDRIN(10:0)totheAddressOutbusADDROUT(10:0).

MemorycontrolsignalsRD/WRandCSarealsopropagated

through the RTI as RRD/RWR and RCS. Input CTRL is

negated during all transparent memory accesses to prevent

the RTI from inadvertently performing an internal register

access or software reset. While CS is asserted, the RTI’s

bidirectional Data bus DATA I/O (15:0) is an input (i.e., not

actively driving bus).

DATA(15:0)

CONTROL

Host

RTI

UT1553B

Shared

Memory

Computer

DATA I/O (15:0)

ADDR OUT (10:0)

ADDR IN (10:0)

DMA

CONTROLLER

Figure 3. Transparent Memory Access Conﬁguration

Control Register (Write Only)

RTI-4

1 2 345 6 7...52

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