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5962-9957601QPA PDF预览

5962-9957601QPA

更新时间: 2024-01-14 07:29:27
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德州仪器 - TI 转换器
页数 文件大小 规格书
23页 679K
描述
2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

5962-9957601QPA 数据手册

 浏览型号5962-9957601QPA的Datasheet PDF文件第7页浏览型号5962-9957601QPA的Datasheet PDF文件第8页浏览型号5962-9957601QPA的Datasheet PDF文件第9页浏览型号5962-9957601QPA的Datasheet PDF文件第11页浏览型号5962-9957601QPA的Datasheet PDF文件第12页浏览型号5962-9957601QPA的Datasheet PDF文件第13页 
TLV5638  
www.ti.com  
SLAS225CJUNE 1999REVISED JANUARY 2004  
APPLICATION INFORMATION  
GENERAL FUNCTION  
The TLV5638 is a dual 12-bit, single supply DAC, based on a resistor string architecture. It consists of a serial  
interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a  
rail-to-rail output buffer.  
The output voltage (full scale determined by reference) is given by:  
CODE  
0x1000  
2 REF  
[V]  
Where REF is the reference voltage and CODE is the digital input value in the range 0x000 to 0xFFF. A power  
on reset initially puts the internal latches to a defined state (all bits zero).  
SERIAL INTERFACE  
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling  
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the  
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.  
Figure 13 shows examples of how to connect the TLV5638 to TMS320, SPI™, and Microwire™.  
TMS320  
DSP  
TLV5638  
SPI  
TLV5638  
CS  
DIN  
Microwire  
I/O  
TLV5638  
CS  
DIN  
CS  
FSX  
DX  
I/O  
MOSI  
SCK  
DIN  
SO  
SK  
CLKX  
SCLK  
SCLK  
SCLK  
Figure 13. Three-Wire Interface  
Notes on SPI™ and Microwire™: Before the controller starts the data transfer, the software has to generate a  
falling edge on the pin connected to CS. If the word width is 8 bits (SPI™ and Microwire™), two write operations  
must be performed to program the TLV5638. After the write operation(s), the holding registers or the control  
register are updated automatically on the 16th positive clock edge.  
SERIAL CLOCK FREQUENCY AND UPDATE RATE  
The maximum serial clock frequency is given by:  
1
) t  
f
+
+ 20 MHz  
sclkmax  
t
whmin  
wlmin  
The maximum update rate is:  
1
f
+
+ 1.25 MHz  
updatemax  
16 ǒt  
Ǔ
) t  
whmin  
wlmin  
Note, that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the  
TLV5638 has to be considered, too.  
10  
 

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