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5962-9957201QYC

更新时间： 2024-01-18 16:35:22

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑
页数	文件大小	规格书
31页	249K
描述
QPro Virtex 2.5V QML High-Reliability FPGAs

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5962-9957201QYC 数据手册

QPro Virtex 2.5V QML High-Reliability FPGAs

IOB Output Switching Characteristics Standard Adjustments

Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust

the delays by the values shown.

Speed Grade

Symbol

Description

Standard

-4

Units

Output Delay Adjustments

T_{OLVTTL_S2}Standard-specific adjustments for output delays

LVTTL, slow

2 mA

4 mA

17.0

8.6

terminating at pads (based on standard capacitive

load, C_sl)

T_{OLVTTL_S4}

T_{OLVTTL_S6}

T_{OLVTTL_S8}

T_{OLVTTL_S12}

T_{OLVTTL_S16}

T_{OLVTTL_S24}

T_{OLVTTL_F2}

T_{OLVTTL_F4}

T_{OLVTTL_F6}

T_{OLVTTL_F8}

T_{OLVTTL_F12}

T_{OLVTTL_F16}

T_{OLVTTL_F24}

T_OLVCMOS2

T_{OPCI33_3}

T_{OPCI33_5}

T_OGTL

6 mA

5.6

8 mA

3.5

12 mA

16 mA

24 mA

2 mA

2.2

2.0

1.6

LVTTL, fast

15.1

6.1

4 mA

6 mA

3.6

8 mA

1.2

12 mA

16 mA

24 mA

0.0

–0.05

–0.23

0.12

2.7

LVCMOS2

PCI, 33 MHz, 3.3V

PCI, 33 MHz, 5.0V

GTL

3.3

0.6

T_OGTLP

GTL+

1.0

T_{OHSTL_I}

HSTL I

–0.5

–1.0

–1.1

–0.5

–1.0

–0.5

–1.1

–0.6

–1.0

T_{OHSTL_III}

T_{OHSTL_IV}

T_{OSSTL2_I}

T_{OSSTL2_II}

T_{OSSTL3_I}

T_{OSSTL3_II}

T_OCTT

HSTL III

HSTL IV

SSTL2 I

SSTL2 II

SSTL3 I

SSTL3 II

CTT

T_OAGP

AGP

www.xilinx.com

1-800-255-7778

DS002 (v1.5) December 5, 2001

Preliminary Product Specification

1...5 6 789 10 11...31

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