Datasheet > 可编程逻辑 > 现场可编程门阵列> 5962-9957201QYC

5962-9957201QYC

更新时间： 2024-02-20 17:11:36

品牌	Logo	应用领域
赛灵思 - XILINX		可编程逻辑
页数	文件大小	规格书
31页	249K
描述
QPro Virtex 2.5V QML High-Reliability FPGAs

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

5962-9957201QYC 数据手册

QPro Virtex 2.5V QML High-Reliability FPGAs

Virtex Switching Characteristics

Testing of switching parameters is modeled after testing

methods specified by MIL-M-38510/605. All devices are

100% functionally tested. Internal timing parameters are

derived from measuring internal test patterns. Listed below

are representative values. For more specific, more precise,

and worst-case guaranteed data, use the values reported

by the static timing analyzer (TRCE in the Xilinx Develop-

ment System) and back-annotated to the simulation netlist.

All timing parameters assume worst-case operating condi-

tions (supply voltage and junction temperature). Values

apply to all Virtex devices unless otherwise noted.

IOB Input Switching Characteristics

Input delays associated with the pad are specified for

LVTTL levels. For other standards, adjust the delays with

the values shown in "IOB Input Switching Characteristics

Standard Adjustments" on page 6.

Speed Grade

-4

Symbol

Propagation Delays

T_IOPI

Description

Device

Min

Max

Units

Pad to I output, no delay

All

1.0

1.9

2.3

2.7

2.0

T_IOPID

Pad to I output, with delay

XQV100

XQV300

XQV600

XQV1000

All

T_IOPLI

Pad to output IQ via transparent latch, no

delay

T_IOPLID

Pad to output IQ via transparent latch, with

delay

XQV100

XQV300

XQV600

XQV1000

4.8

5.1

5.5

5.9

Sequential Delays

T_IOCKIQ

Clock CLK to output IQ

All

0.8

Setup and Hold Times with Respect to Clock CLK

Setup Time / Hold Time

T_IOPICK/ T_IOICKP

Pad, no delay

All

2.0 / 0

5.0 / 0

1.0 / 0

1.3 / 0

_IOPICKD/ T_IOICKPD

_IOICECK/ T_IOCKICE

_IOSRCKI/ T_IOCKISR

Pad, with delay

ICE input

SR input (IFF, synchronous)

Set/Reset Delays

T_IOSRIQ

SR input to IQ (asynchronous)

GSR to output IQ

All

1.8

T_GSRQ

12.5

Notes:

1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”,

but if a “0” is listed, there is no positive hold time.

DS002 (v1.5) December 5, 2001

www.xilinx.com

Preliminary Product Specification

1-800-255-7778

1 2 3 456 7 8...31

下载PDF

与5962-9957201QYC相关器件

型号	品牌	描述	获取价格	数据表
5962-9957201QZA	XILINX	QPro Virtex 2.5V QML High-Reliability FPGAs	获取价格
5962-9957201QZB	XILINX	QPro Virtex 2.5V QML High-Reliability FPGAs	获取价格
5962-9957201QZC	XILINX	QPro Virtex 2.5V QML High-Reliability FPGAs	获取价格
5962-9957201QZX	XILINX	Field Programmable Gate Array, 1536 CLBs, 322970 Gates, CMOS, CQFP228, CERAMIC, QFP-228	获取价格
5962-99573	XILINX	QPro Virtex 2.5V QML High-Reliability FPGAs	获取价格
5962-9957301NNA	XILINX	QPro Virtex 2.5V QML High-Reliability FPGAs	获取价格