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5962-9952102QYX

更新时间： 2024-01-20 01:25:16

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		可编程逻辑输入元件时钟
页数	文件大小	规格书
64页	1733K
描述
EE PLD, 10ns, CMOS, CQCC84, CERAMIC, LCC-84

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5962-9952102QYX 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	84
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.83
最大时钟频率：	83 MHz	长度：	29.21 mm
专用输入次数：	1	I/O 线路数量：	69
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	1 DEDICATED INPUTS, 69 I/O	输出函数：	MACROCELL
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装形式：	CHIP CARRIER	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class Q	座面最大高度：	4.826 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	29.21 mm
Base Number Matches：	1

5962-9952102QYX 数据手册

Ultra37000 CPLD Family

TO CLOCK MUX ON

ALL INPUT MACROCELLS

INPUT/CLOCK PIN

C12

TO CLOCK MUX

IN EACH

LOGIC BLOCK

C13, C14, C15

OR C16

TO PIM

CLOCK POLARITY MUX

ONE PER LOGIC BLOCK

FOR EACH CLOCK INPUT

FROM CLOCK

POLARITY INPUT

CLOCK PINS

C10C11

Figure 4. Input/Clock Macrocell

INPUT PIN

TO PIM

FROM CLOCK

POLARITY MUXES

C12 C13

C10 C11

Figure 3. Input Macrocell

Timing Model

Clockin g

Each I/O and buried macrocell has access to four synchronous

clocks (CLK0, CLK1, CLK2 and CLK3) as well as an

asynchronous product term clock PTCLK. Each input

macrocell has access to all four synchronous clocks.

One of the most important features of the Ultra37000 family is

the simplicity of its timing. All delays are worst case and

system performance is unaffected by the features used. Figure

5 illustrates the true timing model for the 167-MHz devices in

high speed mode. For combinatorial paths, any input to any

output incurs a 6.5-ns worst-case delay regardless of the

amount of logic used. For synchronous systems, the input

set-up time to the output macrocells for any input is 3.5 ns and

the clock to output time is also 4.0 ns. These measurements

are for any output and synchronous clock, regardless of the

logic used.

Dedicated Inputs/Clocks

Five pins on each member of the Ultra37000 family are desig-

nated as input-only. There are two types of dedicated inputs

on Ultra37000 devices: input pins and input/clock pins.

Figure 3 illustrates the architecture for input pins. Four input

options are available for the user: combinatorial, registered,

double-registered, or latched. If a registered or latched option

is selected, any one of the input clocks can be selected for

control.

The Ultra37000 features:

• No fanout delays

• No expander delays

Figure 4 illustrates the architecture for the input/clock pins.

Like the input pins, input/clock pins can be combinatorial,

registered, double-registered, or latched. In addition, these

pins feed the clocking structures throughout the device. The

clock path at the input has user-configurable polarity.

• No dedicated vs. I/O pin delays

• No additional delay through PIM

• No penalty for using 0–16 product terms

• No added delay for steering product terms

• No added delay for sharing product terms

• No routing delays

Product Term Clocking

In addition to the four synchronous clocks, the Ultra37000

family also has a product term clock for asynchronous

clocking. Each logic block has an independent product term

clock which is available to all 16 macrocells. Each product term

clock also supports user configurable polarity selection.

• No output bypass delays

The simple timing model of the Ultra37000 family eliminates

unexpected performance penalties.

Document #: 38-03007 Rev. *D

Page 6 of 64

1...3 4 567 8 9...64

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5962-9952201QYA	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952201QYX	CYPRESS	EE PLD, 15ns, CMOS, CQCC84, CERAMIC, LCC-84	获取价格
5962-9952301QZC	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952302QZC	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
5962-9952401QZC	CYPRESS	5V, 3.3V, ISRTM High-Performance CPLDs	获取价格
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