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5962-9952102QYX

更新时间： 2024-01-28 14:25:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		可编程逻辑输入元件时钟
页数	文件大小	规格书
64页	1733K
描述
EE PLD, 10ns, CMOS, CQCC84, CERAMIC, LCC-84

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技术参数
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5962-9952102QYX 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	84
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.83
最大时钟频率：	83 MHz	长度：	29.21 mm
专用输入次数：	1	I/O 线路数量：	69
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	1 DEDICATED INPUTS, 69 I/O	输出函数：	MACROCELL
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QCCJ
封装形式：	CHIP CARRIER	可编程逻辑类型：	EE PLD
传播延迟：	10 ns	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class Q	座面最大高度：	4.826 mm
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	29.21 mm
Base Number Matches：	1

5962-9952102QYX 数据手册

Ultra37000 CPLD Family

The buried macrocell also supports input register capability.

The buried macrocell can be configured to act as an input

associated with the neighboring macrocell. The output of all

buried macrocells is sent directly to the PIM regardless of its

configuration.

Bus Hold Capabilities on all I/Os

Bus-hold, which is an improved version of the popular internal

pull-up resistor, is a weak latch connected to the pin that does

not degrade the device’s performance. As a latch, bus-hold

maintains the last state of a pin when the pin is placed in a

high-impedance state, thus reducing system noise in

bus-interface applications. Bus-hold additionally allows

unused device pins to remain unconnected on the board,

which is particularly useful during prototyping as designers can

route new signals to the device without cutting trace connec-

tions to V_CCor GND. For more information, see the application

note Understanding Bus-Hold—A Feature of Cypress CPLDs.

I/O Macrocell

Figure 2 illustrates the architecture of the I/O macrocell. The

I/O macrocell supports the same functions as the buried

macrocell with the addition of I/O capability. At the output of the

macrocell, a polarity control mux is available to select active

LOW or active HIGH signals. This has the added advantage

of allowing significant logic reduction to occur in many appli-

cations.

Programmable Slew Rate Control

Each output has a programmable configuration bit, which sets

the output slew rate to fast or slow. For designs concerned with

meeting FCC emissions standards the slow edge provides for

lower system noise. For designs requiring very high perfor-

mance the fast edge rate provides maximum system perfor-

mance.

The Ultra37000 macrocell features a feedback path to the PIM

separate from the I/O pin input path. This means that if the

macrocell is buried (fed back internally only), the associated

I/O pin can still be used as an input.

I/O MACROCELL

FAST

FROM PTM

SLEW

C26

SLOW

0−16

PRODUCT

TERMS

C25

I/O CELL

D/T/L

“0”

“1”

DECODE

C2 C3

C0 C1C24

C6 C5

BURIED MACROCELL

FROM PTM

0−16

PRODUCT

TERMS

C25

D/T/L

DECODE

C2 C3

C0 C1C24

FEEDBACK TO PIM

ASYNCHRONOUS

BLOCK RESET

ASYNCHRONOUS

4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)

1 ASYNCHRONOUS CLOCK(PTCLK)

OE0

OE1

BLOCK PRESET

Figure 2. I/O and Buried Macrocells

Document #: 38-03007 Rev. *D

Page 5 of 64

1 2 3 456 7 8...64

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