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5962-9952502QZC

更新时间： 2024-11-18 22:12:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		可编程逻辑器件输入元件时钟
页数	文件大小	规格书
64页	1733K
描述
5V, 3.3V, ISRTM High-Performance CPLDs

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5962-9952502QZC 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP, QFP208,1.2SQ,20	针数：	208
Reach Compliance Code：	unknown	ECCN代码：	3A001.A.2.C
HTS代码：	8542.39.00.01	风险等级：	5.75
其他特性：	YES	最大时钟频率：	80 MHz
系统内可编程：	YES	JESD-30 代码：	S-CQFP-G208
JESD-609代码：	e4	JTAG BST：	YES
长度：	28 mm	专用输入次数：	1
I/O 线路数量：	165	宏单元数：	512
端子数量：	208	最高工作温度：	125 °C
最低工作温度：	-55 °C	组织：	1 DEDICATED INPUTS, 165 I/O
输出函数：	MACROCELL	封装主体材料：	CERAMIC, METAL-SEALED COFIRED
封装代码：	FQFP	封装等效代码：	QFP208,1.2SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, FINE PITCH
电源：	3.3/5,5 V	可编程逻辑类型：	EE PLD
传播延迟：	12 ns	认证状态：	Qualified
筛选级别：	MIL-PRF-38535 Class Q	座面最大高度：	3.94 mm
子类别：	Programmable Logic Devices	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	GOLD
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	28 mm
Base Number Matches：	1

5962-9952502QZC 数据手册

Ultra37000 CPLD Family

5V, 3.3V, ISR™ High-Performance CPLDs

Features

General Description

• In-System Reprogrammable™ (ISR™) CMOS CPLDs

— JTAG interface for reconfigurability

— Design changes do not cause pinout changes

— Design changes do not cause timing changes

• High density

The Ultra37000™ family of CMOS CPLDs provides a range of

high-density programmable logic solutions with unparalleled

system performance. The Ultra37000 family is designed to

bring the flexibility, ease of use, and performance of the 22V10

to high-density CPLDs. The architecture is based on a number

of logic blocks that are connected by a Programmable Inter-

connect Matrix (PIM). Each logic block features its own

product term array, product term allocator, and 16 macrocells.

The PIM distributes signals from the logic block outputs and all

input pins to the logic block inputs.

— 32 to 512 macrocells

— 32 to 264 I/O pins

— Five dedicated inputs including four clock pins

• Simple timing model

All of the Ultra37000 devices are electrically erasable and

In-System Reprogrammable (ISR), which simplifies both

design and manufacturing flows, thereby reducing costs. The

ISR feature provides the ability to reconfigure the devices

without having design changes cause pinout or timing

changes. The Cypress ISR function is implemented through a

JTAG-compliant serial interface. Data is shifted in and out

through the TDI and TDO pins, respectively. Because of the

superior routability and simple timing model of the Ultra37000

devices, ISR allows users to change existing logic designs

while simultaneously fixing pinout assignments and

maintaining system performance.

— No fanout delays

— No expander delays

— No dedicated vs. I/O pin delays

— No additional delay through PIM

— No penalty for using full 16 product terms

— No delay for steering or sharing product terms

• 3.3V and 5V versions

• PCI-compatible^[1]

The entire family features JTAG for ISR and boundary scan,

and is compatible with the PCI Local Bus specification,

meeting the electrical and timing requirements. The

Ultra37000 family features user programmable bus-hold

capabilities on all I/Os.

• Programmable bus-hold capabilities on all I/Os

• Intelligent product term allocator provides:

— 0 to 16 product terms to any macrocell

— Product term steering on an individual basis

— Product term sharing among local macrocells

• Flexible clocking

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can

support 5V or 3.3V I/O levels. V_CCOconnections provide the

capability of interfacing to either a 5V or 3.3V bus. By

connecting the V_CCOpins to 5V the user insures 5V TTL levels

on the outputs. If V_CCOis connected to 3.3V the output levels

meet 3.3V JEDEC standard CMOS levels and are 5V tolerant.

These devices require 5V ISR programming.

— Four synchronous clocks per device

— Product term clocking

— Clock polarity control per logic block

• Consistent package/pinout offeringacrossall densities

— Simplifies design migration

Ultra37000V 3.3V Devices

— Same pinout for 3.3V and 5.0V devices

• Packages

Devices operating with a 3.3V supply require 3.3V on all V_CCO

pins, reducing the device’s power consumption. These

devices support 3.3V JEDEC standard CMOS output levels,

and are 5V-tolerant. These devices allow 3.3V ISR

programming.

— 44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP,

BGA, and Fine-Pitch BGA packages

— Lead(Pb)-free packages available

Note:

1. Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to V , PCI V = 2V.

Cypress Semiconductor Corporation

Document #: 38-03007 Rev. *D

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised October 25, 2004

12 3 4 5 6 7...64

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5962-9952502QZC 替代型号

型号	品牌	替代类型	描述	数据表
CY37512P208-100UM	CYPRESS	完全替代	5V, 3.3V, ISRTM High-Performance CPLDs
CY37512P208-83NI	CYPRESS	类似代替	5V, 3.3V, ISR⑩ High-Performance CPLDs
CY37512P208-83NC	CYPRESS	类似代替	5V, 3.3V, ISR⑩ High-Performance CPLDs

与5962-9952502QZC相关器件

型号	品牌	获取价格	描述	数据表
5962-9952502QZX	CYPRESS	获取价格	EE PLD, 12ns, CMOS, CQFP208, CERAMIC, QFP-208
5962-9952601QZC	CYPRESS	获取价格	5V, 3.3V, ISRTM High-Performance CPLDs
5962-9952601QZX	CYPRESS	获取价格	EE PLD, 20ns, CMOS, CQFP208, CERAMIC, QFP-208
5962-9952701Q9A	ETC	获取价格	FPGA
5962-9952701QXC	ETC	获取价格	Field Programmable Gate Array (FPGA)
5962-9952701QXX	WEDC	获取价格	Field Programmable Gate Array, 2414 CLBs, 20000 Gates, 115MHz, CMOS, CQFP256, CAVITY-UP, C
5962-9952701QYC	ETC	获取价格	Field Programmable Gate Array (FPGA)
5962-9952702QXC	ETC	获取价格	Field Programmable Gate Array (FPGA)
5962-9952702QYC	ETC	获取价格	Field Programmable Gate Array (FPGA)
5962-9953101MMA	ETC	获取价格	Positive Fixed Voltage Regulator

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