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5962-9561301HYC

更新时间： 2024-02-29 12:40:54
品牌 Logo 应用领域
MICROSS 静态存储器内存集成电路
页数 文件大小 规格书
12页 108K
描述
Standard SRAM, 512KX8, 120ns, CMOS, CDIP32, CERAMIC, DIP-32

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5962-9561301HYC 技术参数

生命周期：Transferred包装说明：CERAMIC, DIP-32
Reach Compliance Code：unknown风险等级：5.59
最长访问时间：120 nsI/O 类型：COMMON
JESD-30 代码：R-CDIP-T32JESD-609代码：e4
长度：41.525 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：32
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：125 °C
最低工作温度：-55 °C组织：512KX8
输出特性：3-STATE封装主体材料：CERAMIC, METAL-SEALED COFIRED
封装代码：DIP封装等效代码：DIP32,.6
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified筛选级别：MIL-STD-883
座面最大高度：5.13 mm最大待机电流：0.0004 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.05 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子面层：GOLD
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：15.24 mm
Base Number Matches：1

5962-9561301HYC 数据手册

 浏览型号5962-9561301HYC的Datasheet PDF文件第2页浏览型号5962-9561301HYC的Datasheet PDF文件第3页浏览型号5962-9561301HYC的Datasheet PDF文件第4页浏览型号5962-9561301HYC的Datasheet PDF文件第5页浏览型号5962-9561301HYC的Datasheet PDF文件第6页浏览型号5962-9561301HYC的Datasheet PDF文件第7页 
SRAM  
AS5C4009LL  
Austin Semiconductor, Inc.  
512K x 8 SRAM  
PIN ASSIGNMENT  
Ultra Low Power SRAM  
(TopView)  
AVAILABLE AS MILITARY  
SPECIFICATION  
• SMD 5962-956131,2  
• MIL STD-8831  
32-Pin DIP, 32-Pin SOJ  
& 32-Pin TSOP  
A18  
A16  
A14  
A12  
A7  
1
2
32  
Vcc  
FEATURES  
• Ultra Low Power with 2V Data Retention  
(0.2mW MAX worst case Power-down standby)  
• Fully Static, No Clocks  
31 A15  
30 A17  
29 WE\  
28 A13  
3
4
• Single +5V ±10% power supply  
• Easy memory expansion with CE\ and OE\ options  
• All inputs and outputs are TTL-compatible  
• Three state outputs  
5
A6  
6
27  
26  
A8  
A9  
A5  
7
A4  
8
25 A11  
24  
• Operating temperature range:  
Ceramic -55oC to +125oC & -40oC to +85oC  
A3  
9
OE\  
Plastic  
-40oC to +85oC3  
A2  
10  
11  
12  
13  
14  
15  
16  
23 A10  
1. Not applicable to plastic package  
2. Applies to CW package only.  
A1  
22  
CE\  
3. Contact factory for -55oC to +125oC  
A0  
21 I/08  
20 I/07  
19 I/06  
18 I/05  
17 I/04  
OPTIONS  
• Timing  
MARKING  
I/01  
I/02  
I/03  
Vss  
55ns access  
70ns access  
85ns access  
-554  
-70  
-85  
100ns access  
• Packages  
Ceramic Dip (600 mil)  
Ceramic SOJ5  
Plastic TSOP  
-100  
CW  
ECJ  
DG  
No. 112  
No. 502  
No. 1002  
4. For DG package, contact factory  
5. Contact Factory  
Pin Name  
WE\  
Function  
NOTE: Not all combinations of operating temperature, speed, data retention and low power are  
necessarily available. Please contact the factory for availability of specific part number  
Write Enable Input  
Chip Select Input  
Output Enable Input  
combinations.  
CE\  
OE\  
GENERAL DESCRIPTION  
The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a  
special ultra low power design process. ASI’s pinout adheres to the  
JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32  
pin version allows for easy upgrades from the 1 meg SRAM design.  
For flexibility in memory applications, ASI offers chip enable (CE\)  
and output enable (OE\) capabilities. These features can place the  
outputs in High-Z for additional flexibility in system design.  
This devices operates from a single +5V power supply and all  
inputs and outputs are fully TTL-compatible.  
A0 - A18 Address Inputs  
I/O1 - I/O8 Data Inputs/Outputs  
Vcc  
Vss  
Power  
Ground  
For more products and information  
please visit our web site at  
www.austinsemiconductor.com  
Writing to these devices is accomplished when write enable (WE\)  
and CE\ inputs are both LOW. Reading is accomplished when WE\  
remains HIGH and CE\ and OE\ go LOW. The device offers a re-  
duced power standby mode when disabled, by lowering VCC to 2V and  
maintaining CE\ = 2V. This allows system designers to meet ultra low  
standby power requirements.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS5C4009LL  
Rev. 4.0 2/01  
1
1234567...12

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